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STMicroelectronics STM32MP135CAF3T
- Part No.:
- STM32MP135CAF3T
- Manufacturer:
- STMicroelectronics
- Category:
- Microprocessors
- Package:
- 320-TFBGA
- Datasheet:
-
STM32MP135CAF3T.pdf
- Description:
- Linear IC's
- Quantity:
- Payment:
- Shipping:
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Product details
Overview
STM32MP135CAF3T from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor operating up to 1 GHz, featuring TrustZone® security, LCD-TFT controller (up to 1920×1080@30 fps), dual Ethernet MAC/GMAC with IEEE 1588v2 hardware support, and dual CAN FD controllers - deployed in industrial HMIs, edge gateways, and secure IoT edge nodes.
For engineers reviewing the STM32MP135CAF3T datasheet, STM32MP135CAF3T pinout, STM32MP135CAF3T application, or STM32MP135CAF3T equivalent, key selection criteria include DDR3/LPDDR3 memory interface timing, TrustZone® peripheral isolation configuration, dual CAN FD bus arbitration latency, and LTDC pixel clock synchronization with external display panels.
Technical Context
The device integrates two Arm Cortex-A7 cores with 128 KB unified L2 cache, NEON™ SIMD acceleration, and TrustZone®-enabled memory protection unit (MPU) for secure world/non-secure world partitioning. Its interconnect matrix comprises a 64-bit AXI bus (266 MHz) and 32-bit AHB bus (209 MHz), enabling concurrent high-bandwidth DDR access and low-latency peripheral control.
Security architecture includes BSEC OTP fuses (3072 bits), AES-256 on-the-fly DRAM encryption, PKA for ECC/RSA with DPA protection, and 12 tamper pins (5 active). Boot flow enforces secure boot via ROM code, verified by SHA-256/SHA-3 hash and HMAC authentication of first-stage bootloader in external flash.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Dual Arm Cortex-A7 @ up to 1 GHz - enables Linux-based real-time applications with deterministic interrupt latency under 1 µs in non-secure mode. |
| Memory Interface | 16-bit DDR3/DDR3L/LPDDR2/LPDDR3-1066 - supports up to 1 Gbyte external SDRAM with hardware ECC for industrial reliability. |
| Graphics Controller | LCD-TFT (LTDC) with 24-bit RGB888 output - drives Full HD (1920×1080) displays at 30 fps with dual programmable layers and secured overlay. |
| Connectivity | 2× CAN FD (ISO 11898-1:2015), 2× Gigabit Ethernet (MII/RMII/RGMII), 2× USB 2.0 HS Host/OTG - enables automotive diagnostics and time-sensitive networking in edge gateways. |
| Analog Peripherals | 2× 12-bit ADCs (5 Msps max), DFSDM with 4 sigma-delta channels, internal temperature sensor - supports motor current sensing and thermal monitoring without external signal conditioning. |
| Security Features | AES-128/192/256 + DPA protection, PKA for ECC-256/RSA-2048, 3072-bit OTP fuses (96-bit UID, 256-bit HUK) - meets IEC 62443-3-3 SL2 requirements for firmware integrity and key protection. |
| Power Management | 5 low-power modes (Sleep, Stop, LPLV-Stop, LPLV-Stop2, Standby), DDR retention in Standby - achieves <15 µA standby current with RTC and backup SRAM active. |
Pinout & Package
STM32MP135CAF3T uses a TFBGA289 (9 × 9 mm, 0.5 mm pitch) package with 289 solder balls. Pin assignment follows B0EB mechanical variant per DS13483 Rev 7 Section 7.2 and Table 7 (ball definitions).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDCORE | Core power supply | 1.1 V ±3% regulated input for CPU and L2 cache - requires low-noise ceramic decoupling within 3 mm of ball. |
| VDDQ_DDR | DDR I/O supply | 1.2 V or 1.35 V supply for DDR data/address bus - must be sequenced after VDDCORE and before VDDIO. |
| NRST | Active-low reset input | Asynchronous reset assertion resets all domains; deassertion triggers POR sequence with internal 10 ms delay. |
| BOOT0 | Boot mode selection | Pulled high during power-up to enable boot from external Quad-SPI flash; level sampled at end of POR timing. |
| ETH1_RXD0–3 | Ethernet receive data | RMII/RGMII-compatible inputs - require 50 Ω series termination and matched trace lengths ≤10 mm for 100 Mbps operation. |
| FDCAN1_TX | CAN FD transmit output | High-speed differential driver (ISO 11898-2 compliant) - connects directly to CAN transceiver TXD pin without external pull-up. |
Key Features
| Feature | Design Value |
|---|---|
| TrustZone®-enabled peripherals | ETZPC configures memory-mapped peripherals as secure/non-secure - isolates crypto engines and tamper detection logic from Linux kernel drivers. |
| Dual Quad-SPI interface | Supports XIP execution from two independent flash devices - enables A/B firmware update with zero downtime in field-deployed gateways. |
| DFSDM with 4 sigma-delta channels | Hardware oversampling and digital filtering - eliminates need for external delta-sigma ADCs in motor control feedback loops. |
| Secure RTC with sub-second accuracy | Hardware calendar and alarm in backup domain - maintains time across full power cycles using VBAT supply and 32.768 kHz LSE crystal. |
| MDMA controller | High-speed master DMA with QoS arbitration - offloads CPU for camera frame transfers (DCMIPP → DDR) at 3 Mpix@30 fps without CPU intervention. |
Applications
| Industrial HMI Panel | Smart Energy Gateway |
|---|---|
Use Scenario: 10-inch capacitive touchscreen HMI running Yocto Linux with Qt5 graphics stack, displaying real-time PLC status and alarm logs. IC Role / Device Role / Timing Role: Main application processor executing Linux kernel, driving LTDC controller for RGB888 interface to display panel, and managing CAN FD communication with field devices. Use Value: Dual Cortex-A7 cores handle GUI rendering and protocol stacks concurrently; LTDC's dual-layer overlay enables secure alarm popups without OS-level privilege escalation. | Use Scenario: DIN-rail mounted gateway aggregating Modbus RTU, CAN FD, and M-Bus meter data, forwarding to cloud via TLS-secured Ethernet. IC Role / Device Role / Timing Role: Secure application host with TrustZone®-isolated crypto engine performing AES-256 encryption of telemetry before transmission over ETH1/ETH2 interfaces. Use Value: On-the-fly DRAM encryption prevents firmware extraction from physical memory dumps; dual Ethernet ports support redundant WAN uplinks with IEEE 1588v2 time sync for synchronized meter reads. |
| Automotive Diagnostic Tool | Secure Edge AI Camera |
Use Scenario: Handheld OBD-II scanner supporting UDS over CAN FD, with Wi-Fi upload of diagnostic trouble codes and ECU flash updates. IC Role / Device Role / Timing Role: Primary MCU executing AUTOSAR-compliant CAN FD stack, managing USB OTG for firmware updates, and controlling SDMMC2 for log storage on eMMC. Use Value: CAN FD bit rate up to 5 Mbps enables rapid ECU reprogramming; secure boot ensures only signed firmware executes, meeting ISO/SAE 21434 requirements. | Use Scenario: IP67-rated surveillance camera capturing 5 Mpix@15 fps monochrome video, performing on-device person detection using TensorFlow Lite Micro. IC Role / Device Role / Timing Role: Vision processing SoC interfacing 8-bit parallel camera sensor via DCMIPP, feeding frames to NEON-accelerated inference engine, and streaming metadata over SPDIF Rx + SAI2 audio interface. Use Value: DCMIPP hardware pipe processes Bayer-to-YUV conversion and noise reduction before CPU load; DFSDM monitors thermal sensor for fan control during sustained AI inference. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core Arm Cortex-A7 microprocessor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXP i.MX 8M Mini (LPC55S69) | Single Cortex-A53 core (1.8 GHz), no TrustZone®-enabled peripherals, lacks CAN FD and LTDC controller | Suitable for audio-centric edge devices but cannot replace STM32MP135CAF3T in CAN FD–based industrial control or TFT display systems | Select only when display interface and automotive bus support are not required; verify software stack compatibility with NXP's Yocto BSP. |
| Renesas RZ/G2L (R9A07G043L220BG) | Dual Cortex-A55 (1.2 GHz), integrated 3D GPU, no hardware AES-256 DRAM encryption or 12-tamper-pin security subsystem | Targets multimedia-rich UIs but lacks the certified security features needed for secure boot in critical infrastructure gateways | Prefer for cost-sensitive consumer UIs; avoid where IEC 62443-3-3 SL2 compliance or on-the-fly memory encryption is mandatory. |
Compared with i.MX 8M Mini and RZ/G2L, STM32MP135CAF3T uniquely combines CAN FD, LTDC, and TrustZone®-enforced DRAM encryption in a single die - making it the only option among the three for secure industrial HMIs requiring simultaneous display, fieldbus, and cryptographic assurance.
Availability
STM32MP135CAF3T is available at Aetrix Electronics and suitable for industrial HMIs, smart energy gateways, automotive diagnostic tools, and secure edge AI cameras requiring stable component supply across multi-year production cycles.
Supply support for STM32MP135CAF3T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog components for industrial, automotive, and consumer markets.
The STM32MP series targets heterogeneous computing in resource-constrained edge devices, combining Linux-capable application cores with real-time microcontroller subsystems - optimized for secure, long-lifecycle industrial and infrastructure applications.
FAQ
What is the maximum supported DDR3L speed and voltage tolerance for STM32MP135CAF3T?
The device supports DDR3L-1066 (533 MHz) with 16-bit data bus width at 1.35 V nominal supply. I/Os are 5 V-tolerant only on designated pins (e.g., certain GPIOs and UART signals); DDR I/Os operate strictly at 1.2 V or 1.35 V and must not exceed ±3% voltage deviation per JEDEC JESD79-4 specification.
Does STM32MP135CAF3T support boot from eMMC, and what initialization sequence is required?
Yes - boot from eMMC is supported via SDMMC1 interface in boot mode 0x03. The ROM code initializes eMMC in HS200 mode, reads the first 512-byte boot sector, and loads FSBL (First Stage Boot Loader) from user area starting at block 0x800. eMMC must be formatted with FAT32 and have BOOT_PARTITION_ENABLE set to 1.
How is TrustZone® enforced for peripheral access, and can secure/non-secure worlds share SRAM?
TrustZone® enforcement is implemented via ETZPC (Embedded TrustZone Protection Controller), which gates AXI transactions to peripherals based on secure/non-secure address space tags. AXI SYSRAM (128 KB) is partitionable: up to 64 KB can be allocated to secure world via TZC configuration; AHB SRAM (32 KB) and Backup SRAM (8 KB) are inherently secure and inaccessible from non-secure world.
What thermal limits apply during sustained 1 GHz CPU operation, and what PCB layout guidance is specified?
At 1 GHz dual-core load, junction temperature must not exceed 105 °C per DS13483 Rev 7 Section 7.4. Recommended layout includes 4 thermal vias (0.3 mm diameter, 0.6 mm pitch) under the exposed pad, 2 oz copper ground plane on inner layers, and minimum 10 mm² copper pour connected to VSS balls. Theta-JA is 27.5 °C/W for TFBGA289 in 4-layer board configuration.
STM32MP135CAF3T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 320-TFBGA
- Series:
- STM32MP1
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A7
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 650MHz
- Co-Processors/DSP:
- Multimedia; NEON™ SIMD
- RAM Controllers:
- DDR3, DDR3L, LPDDR2, LPDDR3
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- LCD
- Ethernet:
- 10/100/1000Mbps (2)
- SATA:
- -
- USB:
- USB 2.0 (2)
- Voltage - I/O:
- 1.8V, 2.5V, 3.3V
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Security Features:
- AES, ARM TZ, Boot Security, Cryptography, Secure Debug, SHA-1/2, Tamper Detection, TRNG, Volatile key Storage
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 320-TFBGA (11x11)
- Additional Interfaces:
- CANbus, GPIO, I2C, I2S, IrDA, MMC/SD/SDIO, SAI, SPDIF, SPI, UART/USART
STM32MP135CAF3T FAQ
1.How can I place an order for STM32MP135CAF3T through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32MP135CAF3T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32MP135CAF3T reliable?
The price and inventory of STM32MP135CAF3T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32MP135CAF3T is usually 5 days.
3.What payment methods are accepted for STM32MP135CAF3T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32MP135CAF3T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32MP135CAF3T?
STM32MP135CAF3T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32MP135CAF3T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32MP135CAF3T?
For technical support, including STM32MP135CAF3T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32MP135CAF3T requirements.
6.How does Aetrix verify that STM32MP135CAF3T is sourced from the original manufacturer or authorized distributors?
All STM32MP135CAF3T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32MP135CAF3T meets industry standards.
7.What is the process for return or replacement of STM32MP135CAF3T?
All STM32MP135CAF3T units undergo pre-shipment inspection (PSI). If there is an issue with STM32MP135CAF3T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32MP135CAF3T part is unused and in its original packaging.
Return procedure for STM32MP135CAF3T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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