STMicroelectronics STM32MP135CAG3

Overview

STM32MP135CAG3 from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor operating up to 1 GHz, featuring TrustZone® security, LCD-TFT controller (up to 1920×1080@30 fps), dual CAN FD, dual Ethernet MAC/GMAC with IEEE 1588v2 support, and hardware crypto acceleration (AES-128/192/256, PKA, HASH). It targets industrial HMI, edge gateway, and secure embedded Linux applications requiring real-time I/O and multimedia capability.

For engineers reviewing the STM32MP135CAG3 datasheet, STM32MP135CAG3 pinout, STM32MP135CAG3 application, or STM32MP135CAG3 equivalent, key selection criteria include DDR3/LPDDR3 memory interface timing, TrustZone-secured peripheral partitioning, camera interface pixel clock (up to 120 MHz), dual CAN FD bit rate (up to 5 Mbps), and thermal performance in LFBGA289 (14×14 mm, 0.8 mm pitch) package.

Technical Context

The STM32MP135CAG3 integrates two Arm Cortex-A7 cores with 32 KB I-cache / 32 KB D-cache per core and a shared 128 KB L2 cache, enabling symmetric multiprocessing under Linux or real-time OS. Its interconnect matrix comprises a 64-bit AXI bus (266 MHz) and 32-bit AHB bus (209 MHz), supporting concurrent high-bandwidth data paths for DDR, camera, and display subsystems.

Security is implemented via hardware-enforced TrustZone address space isolation, BSEC OTP fuses (3072-bit including 96-bit UID and 256-bit HUK), secure boot chain, tamper detection on 12 pins (5 active), and on-the-fly AES-128 DRAM encryption. The dual ADC subsystem supports 12-bit resolution at 5 Msps with DFSDM sigma-delta filtering for sensor signal conditioning.

Key Specifications

Pinout & Package

LFBGA289 (14 × 14 mm, 0.8 mm pitch) package with 289 balls, ECOPACK2 compliant. Ball map defined per DS13483 Rev 7 Section 4 (Pinout, pin description and alternate functions) and Table 7 (ball definitions).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core Arm A-class microprocessor applications.

Compared with i.MX 8M Mini and RZ/G2L, the STM32MP135CAG3 uniquely combines dual Cortex-A7 with industrial-grade security (tamper pins, HUK, BSEC OTP), dual CAN FD, and dual Gigabit Ethernet in a single LFBGA289 package - making it optimal for certified edge gateways where functional safety and cybersecurity are co-required.

Availability

STM32MP135CAG3 is available at Aetrix Electronics and suitable for industrial HMI, secure edge gateways, embedded vision terminals, and audio-enabled IoT appliances requiring stable component supply across multi-year production cycles.

Supply support for STM32MP135CAG3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in microcontrollers, power management, and automotive ICs with strong industrial and security IP portfolios.

The STM32MP series targets Linux-capable heterogeneous computing for industrial, building automation, and edge AI applications - balancing real-time responsiveness, security assurance, and power efficiency in a single-chip solution.

FAQ

What boot sources does the STM32MP135CAG3 support?

The STM32MP135CAG3 supports boot from eMMC, SD card, SPI NOR flash, and NAND flash via its flexible boot ROM. Boot mode is selected by strapping BOOT0 and BOOT1 pins at power-on reset, and the device executes a verified secure boot chain using BSEC OTP keys and TrustZone-protected ROM code before loading FSBL from external media.

Does the STM32MP135CAG3 include hardware debug support?

Yes - it features Arm CoreSight™ debug infrastructure with SWD and JTAG interfaces, both usable as general-purpose GPIOs after debug initialization. A 4-Kbyte embedded trace buffer enables real-time instruction tracing, and debug access is gated by TrustZone security state to prevent unauthorized firmware inspection.

What is the maximum pixel clock frequency supported by the camera interface?

The DCMIPP camera interface supports a maximum pixel clock of 120 MHz, enabling capture of 3 Mpix color images at 30 fps or 5 Mpix monochrome images at 15 fps. This timing is validated per DS13483 Rev 7 Section 6.3.32 and requires matched PCB trace lengths and proper termination for parallel 8–16-bit data buses.

How is DDR memory retention managed during low-power modes?

In Standby mode, the STM32MP135CAG3 maintains DDR memory contents using internal retention logic while powering down CPU, caches, and most peripherals. This is enabled by the backup regulator (~0.9 V) and controlled via the PWR_CR3 register; DDR self-refresh remains active, allowing sub-100 µs wakeup latency to resume Linux execution from saved context.