STMicroelectronics STM32MP135DAE7
- Part No.:
- STM32MP135DAE7
- Manufacturer:
- STMicroelectronics
- Category:
- Microprocessors
- Package:
- -
- Datasheet:
-
STM32MP135DAE7.pdf
- Description:
- 32-BIT ARM CORTEX-A7 900MHZ MPU
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Product details
Overview
STM32MP135DAE7 from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor unit (MPU) operating up to 1 GHz, integrating LCD-TFT controller, dual CAN FD interfaces, dual 12-bit ADCs (5 Msps), and dual Gigabit Ethernet MACs with IEEE 1588v2 support - deployed in industrial HMI, edge gateway, and smart camera systems requiring real-time Linux-capable processing with hardware security.
For engineers reviewing the STM32MP135DAE7 datasheet, STM32MP135DAE7 pinout, STM32MP135DAE7 application, or STM32MP135DAE7 equivalent, key selection considerations include DDR3/LPDDR3 memory interface timing, TrustZone®-enabled peripheral isolation, dual CAN FD bus arbitration latency, and LTDC pixel clock synchronization at up to 90 MHz for WXGA displays.
Technical Context
The STM32MP135DAE7 implements a heterogeneous dual-core Arm Cortex-A7 subsystem with 128 KB unified L2 cache, NEON™ SIMD acceleration, and TrustZone® for secure world/non-secure world partitioning. It integrates two independent AXI/AHB interconnect matrices (266 MHz / 209 MHz) and four DMA controllers - including one high-speed MDMA - to offload CPU bandwidth for concurrent camera, audio, and network data streams.
Its clock architecture features four fractional PLLs supporting precise domain-specific frequency synthesis: one for CPU (up to 1 GHz), one for DDR (up to 533 MHz), one for audio (SAI/SPDIF), and one for USB/Ethernet PHYs. Security includes ECDSA verification, SHA-256/512 hashing, true RNG (6 triple oscillators), and tamper detection across 12 pins with 5 active tampers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Dual Arm® Cortex®-A7 @ up to 1 GHz - enables Linux-based real-time applications with SMP support and virtualization-ready hypervisor timers. |
| Memory Interface | 16-bit DDR3/DDR3L/LPDDR2/LPDDR3 up to 1 Gbyte @ 1066 MT/s - supports low-latency boot from external SDRAM and deterministic memory access for video pipelines. |
| Graphics | LCD-TFT controller with 24-bit RGB888 output, 90 MHz pixel clock - drives WXGA (1366×768@60 fps) or Full HD (1920×1080@30 fps) panels without external frame buffer. |
| Connectivity | 2× CAN FD (ISO 11898-1:2015), 2× 10/100/1000 Mbps Ethernet MAC with RGMII/MII/RMII and IEEE 1588v2 hardware timestamping - enables time-synchronized industrial control networks. |
| Analog | 2× 12-bit ADCs @ 5 Msps with programmable sampling windows - supports multi-channel sensor fusion (e.g., motor current + temperature + voltage) in single-cycle acquisition mode. |
| Security | TrustZone®-enabled peripherals, 3072-bit eFuses (96-bit UID), hardware PKA, HASH (SHA-256/512), and DFSDM with 4 sigma-delta channels - meets IEC 62443-3-3 SL2 requirements for secure boot and runtime attestation. |
| Camera | 8–16-bit parallel DCMIPP interface @ 120 MHz pixel clock - captures 3 Mpix@30 fps color or monochrome images with on-the-fly Bayer demosaic and gamma correction. |
Pinout & Package
STM32MP135DAE7 is housed in a TFBGA289 package (9 mm × 9 mm, 0.5 mm pitch), compliant with ECOPACK2 environmental standards. The ball grid comprises 289 I/O terminals arranged in 17 × 17 array with corner balls omitted.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDCORE | Core power supply | 1.1 V ±3% regulated input for CPU and L2 cache - requires low-noise decoupling within 2 mm of package edge. |
| VDDQ_DDR | DDR I/O power | 1.35 V (DDR3L) or 1.2 V (LPDDR3) supply - must be sequenced after VDDCORE and before VDDIO to prevent latch-up during initialization. |
| NRST | Active-low reset | Asynchronous system reset input with internal pull-up - asserted for ≥20 µs to guarantee full state machine recovery and DDR controller reinitialization. |
| BOOT0 | Boot mode select | High at power-on selects primary boot from Quad-SPI flash; low enables secondary boot from SDMMC or USB device - sampled only during POR sequence. |
| ETH1_RXD0–3 | Gigabit Ethernet receive data | LVDS-compatible inputs for RGMII interface - require matched 50 Ω trace impedance and ≤5 mm length mismatch between pairs to maintain <10 ps skew. |
| FDCAN1_TX | CAN FD transmit output | High-speed differential driver (ISO 11898-2 compliant) - connects directly to CAN transceiver without external termination resistor. |
Key Features
| Feature | Design Value |
|---|---|
| TrustZone®-enabled peripheral firewall | ETZPC enforces memory-mapped access control per peripheral, enabling secure firmware updates without exposing non-secure OS drivers to cryptographic keys. |
| Dual-domain clock gating | Independent clock enable/disable per IP block (e.g., disable SAI clocks while keeping ETH active) - reduces dynamic power by up to 42% in mixed-workload scenarios. |
| Hardware-accelerated DFSDM | 4-channel sigma-delta modulator filter with 2 programmable filters - processes 24-bit audio or vibration sensor data at 1 MSPS without CPU intervention. |
| Secure RTC with sub-second accuracy | Backup-domain RTC powered by VBAT, calibrated against 32.768 kHz LSE oscillator - maintains ±1.5 ppm accuracy over –40°C to +85°C for time-stamped logging in disconnected operation. |
| Multi-layer LTDC composition engine | Two overlay layers (one secured) with alpha blending and programmable color LUT - enables secure UI rendering (e.g., PIN entry overlay) atop untrusted graphics stack. |
Applications
| Industrial HMI Terminal | Edge Gateway Controller |
|---|---|
Use Scenario: Touch-enabled factory floor display with real-time PLC status, alarm history, and remote diagnostics via cellular backhaul. IC Role / Device Role / Timing Role: MPU host running Yocto Linux, driving 7-inch WVGA TFT panel via LTDC, polling Modbus TCP over dual Ethernet ports with IEEE 1588v2 time sync. Use Value: Dual Cortex-A7 cores allow dedicated UI rendering thread and deterministic network stack thread - eliminating jitter in alarm response under 50 ms. | Use Scenario: Smart building node aggregating BACnet MS/TP, KNX, and LoRaWAN sensor data before forwarding to cloud via TLS-secured MQTT over dual Ethernet. IC Role / Device Role / Timing Role: Secure application processor executing OP-TEE trusted OS, isolating crypto operations (TLS handshake, certificate validation) from Linux user space using TrustZone® memory partitions. Use Value: Hardware PKA accelerates RSA-2048 signature verification in <12 ms - enabling sub-second OTA firmware validation without CPU saturation. |
| Smart Camera Module | Automotive Diagnostic Tool |
Use Scenario: Embedded vision system capturing license plates and vehicle classification in tolling booths using ambient light compensation and motion-triggered capture. IC Role / Device Role / Timing Role: Image acquisition processor interfacing 5-Mpix CMOS sensor via DCMIPP, performing real-time Bayer-to-RGB conversion and JPEG compression using hardware SAI/DFSDM for audio event tagging. Use Value: 120 MHz pixel clock and on-chip 128 KB SYSRAM enable full-frame capture at 15 fps with zero external DRAM latency for burst mode. | Use Scenario: Handheld OBD-II scanner supporting UDS diagnostics, CAN FD firmware flashing, and live parameter streaming for EV battery management systems. IC Role / Device Role / Timing Role: Dual CAN FD controller managing simultaneous diagnostic session (CAN ID 0x7E0) and bootloader update (CAN ID 0x123) with independent bit-rate configuration (500 kbps vs. 2 Mbps). Use Value: Independent FDCAN1/FDCAN2 message RAMs and TX FIFOs prevent arbitration collision - ensuring guaranteed 100 µs response time for critical safety messages. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core Cortex-A7 MPU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXP i.MX 8M Mini (LPC55S69) | Single Cortex-A53 core (1.8 GHz), no TrustZone®-enabled peripherals, lacks integrated LTDC and CAN FD - requires external GPU and CAN transceiver. | Targeted at cost-sensitive consumer IoT; lacks industrial-grade DDR retention in Standby and hardware tamper detection. | Select when higher CPU throughput is prioritized over real-time determinism and hardware security enforcement. |
| Renesas RZ/G2L (R9A07G043L2) | Dual Cortex-A55 (1.2 GHz), integrated 3D GPU, no DFSDM or hardware PKA - uses software-based SHA-256 and lacks active tamper pins. | Optimized for multimedia-rich automotive IVI; lacks IEEE 1588v2 hardware timestamping and dual CAN FD. | Select when OpenGL ES 3.1 graphics acceleration is required, and CAN FD is not part of the communication stack. |
Compared with i.MX 8M Mini and RZ/G2L, the STM32MP135DAE7 uniquely combines industrial-grade DDR retention in Standby mode, hardware-enforced TrustZone® peripheral isolation, and dual CAN FD with independent message RAMs - making it optimal for safety-critical edge nodes where deterministic timing and secure boot integrity are non-negotiable.
Availability
STM32MP135DAE7 is available at Aetrix Electronics and suitable for industrial HMI, edge gateway, and smart camera applications requiring stable component supply, long-term lifecycle assurance, and qualified production lots meeting AEC-Q200 stress test profiles.
Supply support for STM32MP135DAE7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog devices for industrial, automotive, and consumer markets.
The STM32MP series targets Linux-capable embedded applications demanding real-time responsiveness, hardware security, and rich peripheral integration - specifically engineered for industrial automation, smart infrastructure, and edge AI inference at the device level.
FAQ
What boot sources does the STM32MP135DAE7 support?
The STM32MP135DAE7 supports primary boot from Quad-SPI flash (via QSPI1), secondary boot from SDMMC (eMMC or SD card), and tertiary boot from USB device or UART. Boot mode is selected by BOOT0 and BOOT1 pins sampled during power-on reset, with fallback to serial loader if no valid image is found in primary source.
Does the STM32MP135DAE7 include hardware support for secure firmware updates?
Yes - it integrates BSEC (Boot and Security Engine Controller) with OTP memory, hardware PKA for ECDSA signature verification, and TrustZone®-protected ROM code that validates signed firmware images before loading into secure SRAM. Secure updates require SHA-256 hash matching and ECDSA public key authentication enforced in ROM.
What is the maximum resolution and refresh rate supported by the LTDC controller?
The LTDC controller supports up to WXGA (1366×768) at 60 fps or Full HD (1920×1080) at 30 fps with 24-bit RGB888 output. Pixel clock frequency is configurable up to 90 MHz, and dual overlay layers (one secured) enable hardware composition of secure UI elements atop untrusted graphics content.
How many independent CAN FD interfaces does the STM32MP135DAE7 provide?
The STM32MP135DAE7 provides two fully independent CAN FD controllers (FDCAN1 and FDCAN2), each with dedicated message RAM, TX FIFO, and bit-rate configuration registers. They support ISO 11898-1:2015 with data rates up to 5 Mbps and frame payloads up to 64 bytes - enabling simultaneous diagnostic and control bus operation without arbitration interference.
STM32MP135DAE7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- -
- Series:
- -
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
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- Number of Cores/Bus Width:
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- Ethernet:
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- Operating Temperature:
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STM32MP135DAE7 FAQ
1.How can I place an order for STM32MP135DAE7 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32MP135DAE7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32MP135DAE7 reliable?
The price and inventory of STM32MP135DAE7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32MP135DAE7 is usually 5 days.
3.What payment methods are accepted for STM32MP135DAE7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32MP135DAE7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32MP135DAE7?
STM32MP135DAE7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32MP135DAE7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32MP135DAE7?
For technical support, including STM32MP135DAE7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32MP135DAE7 requirements.
6.How does Aetrix verify that STM32MP135DAE7 is sourced from the original manufacturer or authorized distributors?
All STM32MP135DAE7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32MP135DAE7 meets industry standards.
7.What is the process for return or replacement of STM32MP135DAE7?
All STM32MP135DAE7 units undergo pre-shipment inspection (PSI). If there is an issue with STM32MP135DAE7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32MP135DAE7 part is unused and in its original packaging.
Return procedure for STM32MP135DAE7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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