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STMicroelectronics STM32MP135DAG7
- Part No.:
- STM32MP135DAG7
- Manufacturer:
- STMicroelectronics
- Category:
- Microprocessors
- Package:
- -
- Datasheet:
-
STM32MP135DAG7.pdf
- Description:
- 32-BIT ARM CORTEX-A7 900MHZ MPU
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Inventory:150
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Product details
Overview
STM32MP135DAG7 from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor unit (MPU) operating up to 1 GHz, integrating LCD-TFT controller, dual CAN FD interfaces, dual 12-bit ADCs (5 Msps), and dual 10/100/1000 Mbps Ethernet MACs with IEEE 1588v2 support - deployed in industrial HMIs, edge gateways, and smart building controllers requiring real-time Linux-capable processing with hardware security.
For engineers reviewing the STM32MP135DAG7 datasheet, STM32MP135DAG7 pinout, STM32MP135DAG7 application, or STM32MP135DAG7 equivalent, key selection criteria include TrustZone®-enabled secure boot, DDR3/LPDDR3 memory controller compatibility, 289-ball LFBGA package thermal profile, and dual-camera interface timing for vision-enabled IoT edge nodes.
Technical Context
The STM32MP135DAG7 implements a dual-core Arm Cortex-A7 subsystem with 128 KB unified L2 cache, NEON™ SIMD acceleration, and TrustZone®-secured peripheral isolation. It features two independent bus matrices (64-bit AXI at 266 MHz, 32-bit AHB at 209 MHz) enabling concurrent high-bandwidth DDR access and low-latency peripheral control.
Its clock architecture includes four fractional PLLs supporting precise audio (SAI/I2S), video (LTDC pixel clock up to 90 MHz), and network (Ethernet PTP) timing domains. Security is enforced via ETZPC, TZC, BSEC OTP fuses, and hardware-accelerated HASH/RNG/PKA engines compliant with NIST SP800-90B/C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Dual Arm Cortex-A7 @ up to 1 GHz - enables Linux-based real-time applications with SMP scheduling and virtualization-ready hypervisor timers. |
| Memory Interface | 16-bit DDR3/DDR3L/LPDDR2/LPDDR3 controller up to 1 Gbyte - supports cost-optimized external SDRAM for embedded Linux workloads. |
| Security | TrustZone® + 12 tamper pins + 3072-bit eFuses (96-bit UID) - provides hardware root-of-trust, secure boot enforcement, and anti-tamper detection for industrial firmware integrity. |
| Graphics | LCD-TFT controller with dual layers (1 secured), RGB888, up to 1920×1080@30 fps - drives high-resolution industrial displays without external GPU. |
| Connectivity | 2× CAN FD, 2× Gigabit Ethernet (MII/RMII/RGMII), 5× I2C, 4× UART/USART, 5× SPI - meets deterministic fieldbus and time-sensitive networking requirements. |
| Analog | 2× 12-bit ADCs (5 Msps), DFSDM (4-channel sigma-delta filter), temperature sensor - supports multi-sensor data acquisition in predictive maintenance systems. |
| Package | LFBGA289 (14 × 14 mm, 0.8 mm pitch) - optimized for thermal dissipation in fanless industrial enclosures with IPC-grade reliability. |
Pinout & Package
LFBGA289 (14 × 14 mm, 0.8 mm pitch) package with 289 solder balls, ECOPACK2-compliant, rated for industrial temperature range (–40 °C to +125 °C junction).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDCORE | Core power supply | 1.0 V ±5% regulated input for CPU/SOC logic; requires low-noise decoupling per ST AN5213 guidelines. |
| VDDQ_DDR | DDR I/O power | 1.2 V or 1.35 V supply for DDR3/LPDDR3 interface; separate rail critical for signal integrity and timing margin. |
| NRST | Active-low reset input | Asynchronous system reset with internal pull-up; compatible with PMIC reset sequencing and watchdog recovery paths. |
| BOOT0 | Boot mode selection | Strapped high/low to select primary boot source (eMMC, SD, QSPI, USB) during power-on reset sequence. |
| ETH1_RX_CLK | Ethernet receive clock | Input clock for ETH1 RMII interface; must be 50 MHz ±50 ppm when using external PHY with RGMII timing constraints. |
| FDCAN1_TX | CAN FD transmit output | High-speed differential CAN FD signal (up to 5 Mbps); requires ISO 11898-2 compliant transceiver and common-mode choke. |
Key Features
| Feature | Design Value |
|---|---|
| Secure Boot with Hardware Root of Trust | Enforced via BSEC OTP fuses and ETZPC-controlled ROM code execution - prevents unauthorized firmware loading and runtime privilege escalation. |
| Dual Independent Bus Matrices | 64-bit AXI (266 MHz) + 32-bit AHB (209 MHz) - eliminates memory/peripheral contention in multi-threaded Linux applications with concurrent display, camera, and network I/O. |
| Hardware Cryptographic Acceleration | HASH (SHA-256/512), RNG (NIST SP800-90B/C), PKA (ECDSA verify) - offloads TLS 1.3 handshake and firmware signature verification from CPU, reducing latency by >80% vs software-only. |
| Flexible Camera Interface (DCMIPP) | 8–16-bit parallel interface supporting 3 Mpix@30 fps color or 5 Mpix@15 fps monochrome - enables direct CMOS sensor integration without FPGA bridging in machine vision edge nodes. |
| Low-Power State Retention | DDR retention in Standby mode with ~15 µA VBAT current - maintains full system context across extended sleep periods in battery-backed industrial gateways. |
Applications
| Industrial HMI | Smart Building Gateway |
|---|---|
Use Scenario: Touchscreen panel controlling HVAC, lighting, and access systems in commercial buildings. IC Role / Device Role / Timing Role: Main application processor running Yocto Linux with Qt-based UI, driving 1366×768 LCD-TFT display at 60 fps and managing CAN FD fieldbus communication. Use Value: Integrated LTDC and dual CAN FD eliminate external display controller and protocol bridge ICs, reducing BOM count and PCB layer count by 2–3 layers. |
Use Scenario: Edge gateway aggregating Modbus, KNX, and BACnet devices into cloud-connected MQTT infrastructure. IC Role / Device Role / Timing Role: Dual Ethernet MACs handle segregated LAN/WAN traffic with IEEE 1588v2 timestamping for synchronized sensor data ingestion. Use Value: Hardware-accelerated SHA-256 and ECDSA verification ensures secure OTA firmware updates without CPU overhead, meeting UL 2900-1 cybersecurity certification requirements. |
| Edge Vision Node | Programmable Logic Controller (PLC) CPU Module |
Use Scenario: Real-time defect detection on production line using monochrome CMOS camera and lightweight CNN inference. IC Role / Device Role / Timing Role: DCMIPP captures 5 Mpix@15 fps image stream; Cortex-A7 cores execute TensorFlow Lite Micro with NEON-optimized kernels. Use Value: On-chip DFSDM and ADCs enable simultaneous analog sensor monitoring (temperature, vibration) alongside vision processing - no external ADC or digital isolator required. |
Use Scenario: Modular PLC backplane CPU card executing IEC 61131-3 ladder logic with deterministic I/O scanning. IC Role / Device Role / Timing Role: Secure RTC with sub-second accuracy and dual watchdogs (IWDG1/IWDG2) enforce hard real-time cycle supervision and safe state recovery. Use Value: TrustZone®-isolated secure world hosts safety-critical runtime monitor, while non-secure world runs standard Linux OS - satisfies IEC 61508 SIL2 functional safety partitioning. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar MPU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32MP157C-DK2 | Same dual Cortex-A7 core but higher L2 cache (256 KB), no integrated DFSDM, lower max DDR bandwidth (LPDDR2 only). | Targeted at GUI-rich consumer panels; lacks industrial-grade tamper pins and backup domain SRAM for safety-critical logging. | Select when prioritizing display performance over analog sensor fusion and security certification evidence. |
| i.MX 8M Mini (NXP) | Quad Cortex-A53 + Cortex-M4, no TrustZone®-secured peripherals, different DDR controller (LPDDR4 only), larger TFBGA485 package. | Optimized for multimedia streaming; lacks dedicated industrial interfaces like CAN FD and fails to meet ST's -40°C to +125°C junction rating. | Choose for Android-based edge AI where ARMv8-A instruction set and GPU acceleration outweigh deterministic I/O and extended temperature needs. |
Compared with STM32MP135DAG7, the STM32MP157C-DK2 offers higher graphics throughput but reduced analog integration and security granularity, while the i.MX 8M Mini delivers broader CPU performance at the cost of industrial interface support, thermal robustness, and hardware-enforced trust boundaries.
Availability
STM32MP135DAG7 is available at Aetrix Electronics and suitable for industrial HMIs, smart building gateways, edge vision nodes, and programmable logic controller CPU modules requiring stable component supply across 10+ year product lifecycles.
Supply support for STM32MP135DAG7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive-grade processors since 1987.
The STM32MP series targets Linux-capable embedded applications demanding real-time responsiveness, hardware security, and industrial interface integration - bridging the gap between microcontrollers and application processors.
FAQ
What boot sources does the STM32MP135DAG7 support?
The STM32MP135DAG7 supports primary boot from eMMC, SD card, Quad-SPI NOR flash, and USB mass storage via configurable BOOT0/BOOT1 pins. Secondary boot options include NAND flash through FMC and serial interfaces using ST's TF-A (Trusted Firmware-A) bootloader with verified boot chain and hash-based image validation.
Does the STM32MP135DAG7 require an external PMIC?
Yes - while the device integrates LDOs for USB PHY (1.8 V) and core (1.1 V), it relies on an external PMIC (e.g., STPMIC1) to generate VDDCORE, VDDQ_DDR, VDDIO, and VBAT rails with sequencing, monitoring, and dynamic voltage scaling. The PMIC interface uses I2C and dedicated control signals per UM2557 reference design.
How is TrustZone® implemented on this MPU?
TrustZone® is implemented at both system and peripheral levels: the ETZPC enforces secure/non-secure access to memories and peripherals; the TZC gates DDR access; and the secure monitor firmware (in ROM) validates all secure world transitions. Critical registers (RNG, HASH, PKA) reside exclusively in secure address space and are inaccessible from non-secure Linux.
What is the maximum camera resolution supported by the DCMIPP interface?
The DCMIPP interface supports up to 5 megapixels at 15 fps in monochrome mode or 3 megapixels at 30 fps in color mode, with pixel clock up to 120 MHz. It accepts 8–16-bit parallel CMOS/CCD sensor outputs and includes on-the-fly Bayer demosaicing, gamma correction, and histogram generation - all configurable via register-mapped DMA descriptors.
STM32MP135DAG7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- -
- Series:
- -
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
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- Number of Cores/Bus Width:
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- Speed:
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- Co-Processors/DSP:
- -
- RAM Controllers:
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- Graphics Acceleration:
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- Display & Interface Controllers:
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- Ethernet:
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- SATA:
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- USB:
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- Voltage - I/O:
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- Operating Temperature:
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- Grade:
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- Security Features:
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- Supplier Device Package:
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STM32MP135DAG7 FAQ
1.How can I place an order for STM32MP135DAG7 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32MP135DAG7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32MP135DAG7 reliable?
The price and inventory of STM32MP135DAG7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32MP135DAG7 is usually 5 days.
3.What payment methods are accepted for STM32MP135DAG7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32MP135DAG7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32MP135DAG7?
STM32MP135DAG7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32MP135DAG7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32MP135DAG7?
For technical support, including STM32MP135DAG7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32MP135DAG7 requirements.
6.How does Aetrix verify that STM32MP135DAG7 is sourced from the original manufacturer or authorized distributors?
All STM32MP135DAG7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32MP135DAG7 meets industry standards.
7.What is the process for return or replacement of STM32MP135DAG7?
All STM32MP135DAG7 units undergo pre-shipment inspection (PSI). If there is an issue with STM32MP135DAG7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32MP135DAG7 part is unused and in its original packaging.
Return procedure for STM32MP135DAG7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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