STMicroelectronics STM32MP135FAE7T

Overview

STM32MP135FAE7T from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor operating up to 1 GHz, integrating LCD-TFT controller (up to Full HD @30 fps), dual CAN FD interfaces, dual 12-bit ADCs (5 Msps), and hardware crypto accelerators (AES-256, PKA, SHA-512). It targets industrial HMI, edge gateway, and secure IoT gateway applications requiring real-time I/O, display, and network connectivity.

For engineers reviewing the STM32MP135FAE7T datasheet, STM32MP135FAE7T pinout, STM32MP135FAE7T application, or STM32MP135FAE7T equivalent, key selection considerations include DDR3/LPDDR3 memory interface support, TrustZone®-enabled secure boot, dual Ethernet MAC with IEEE 1588v2, camera interface (3 Mpix @30 fps), and 135 secure GPIOs with tamper detection.

Technical Context

The STM32MP135FAE7T implements a heterogeneous dual-core Arm Cortex-A7 subsystem with 128 KB unified L2 cache, NEON™ SIMD support, and TrustZone® for hardware-enforced isolation between secure and non-secure worlds. Its interconnect includes a 64-bit AXI bus matrix (266 MHz) and 32-bit AHB matrix (209 MHz), enabling concurrent high-bandwidth peripheral access.

It integrates dual independent FDCAN controllers compliant with ISO 11898-1:2015 (CAN FD), supporting data rates up to 5 Mbit/s and payloads up to 64 bytes. The LCD-TFT controller supports RGB888 (24-bit) output with dual programmable layers, pixel clock up to 90 MHz, and hardware-accelerated alpha blending - critical for responsive industrial GUIs.

Key Specifications

Pinout & Package

STM32MP135FAE7T is housed in a TFBGA289 package (9 × 9 mm, 0.5 mm ball pitch), with 289 I/O balls arranged in a 17 × 17 grid. Ball definitions follow ST's standard mapping per DS13483 Rev 7 Section 4 (Pinout and alternate functions), including dedicated power domains (VDDCORE, VDDCPU, VDDQ_DDR), multiple I/O voltage groups (1.71–3.6 V, 5 V-tolerant), and dedicated TrustZone®-protected signal lines.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core Arm A-class processor applications.

Compared with NXP i.MX 8M Mini and Renesas RZ/G2L, the STM32MP135FAE7T uniquely combines TrustZone®-enforced secure boot, on-the-fly AES-256 DRAM encryption, integrated LCD-TFT controller, and dual FDCAN - reducing BOM count and PCB area while meeting IEC 62443-3-3 SL2 requirements out-of-box.

Availability

STM32MP135FAE7T is available at Aetrix Electronics and suitable for industrial HMI, secure edge gateway, and medical diagnostic display applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for STM32MP135FAE7T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in microcontrollers, power management, sensors, and automotive ICs with strong focus on industrial and embedded markets.

The STM32MP series is ST's heterogeneous multicore MPUs designed specifically for Linux-capable edge devices requiring real-time responsiveness, rich graphics, and hardware-enforced security - bridging the gap between microcontrollers and application processors.

FAQ

What boot sources does the STM32MP135FAE7T support?

The STM32MP135FAE7T supports boot from eMMC, SD card, SPI NOR flash, Quad-SPI NOR flash, NAND flash, and USB mass storage via its ROM bootloader. Boot mode is selected using BOOT0 and BOOT1 pins at power-on reset, and the first-stage bootloader (FSBL) validates digital signatures before loading the second-stage bootloader (SSBL).

Does the STM32MP135FAE7T include hardware debug support?

Yes - it integrates Arm CoreSight™ debug infrastructure with SWD and JTAG interfaces, both usable as general-purpose GPIOs when debug is disabled. It includes a 4-Kbyte embedded trace buffer and supports secure debug authentication via TrustZone®-protected debug access ports.

How is DDR memory managed for security and performance?

The STM32MP135FAE7T uses a TrustZone Address Space Controller (TZC) to enforce memory access permissions for DDR regions, and its SAES engine performs on-the-fly AES-256 encryption/decryption of all DDR read/write traffic using keys derived from the 256-bit Hardware Unique Key (HUK), preventing unauthorized access to external memory contents.

What camera sensor interfaces are supported?

The STM32MP135FAE7T features a dedicated Digital Camera Interface Pipe Processing (DCMIPP) block supporting 8–16-bit parallel CMOS/CCD sensors at up to 120 MHz pixel clock - enabling 3 Mpix @30 fps (color) or 5 Mpix @15 fps (monochrome) - with built-in pipeline stages for Bayer demosaic, gamma correction, and histogram generation.