STMicroelectronics STM32MP135FAF7T

Overview

STM32MP135FAF7T from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor operating up to 1 GHz, integrating LCD-TFT controller, dual CAN FD interfaces, dual 12-bit ADCs (5 Msps), and hardware crypto acceleration (AES-128/192/256, PKA, HASH). It targets industrial HMI, edge gateway, and secure embedded Linux systems requiring real-time camera capture (3 Mpix @30 fps), dual Ethernet (IEEE 1588v2), and TrustZone®-enabled secure boot.

For engineers reviewing the STM32MP135FAF7T datasheet, STM32MP135FAF7T pinout, STM32MP135FAF7T application, or STM32MP135FAF7T equivalent, key selection criteria include DDR3/LPDDR3 memory interface support, 289-ball LFBGA package with 0.8 mm pitch, dual 12-bit ADC performance, TrustZone® peripheral isolation, and verified CAN FD timing compliance per ISO 11898-1:2015.

Technical Context

The device implements a heterogeneous dual-core Arm Cortex-A7 subsystem with 128 KB unified L2 cache, NEON™ SIMD engine, and TrustZone® security extensions for hardware-enforced memory and peripheral partitioning. It features two independent bus matrices (64-bit AXI at 266 MHz, 32-bit AHB at 209 MHz) enabling concurrent high-bandwidth DDR access and low-latency peripheral control.

Clock management includes four fractional PLLs supporting precise frequency synthesis for USB HS (480 MHz), Ethernet (125 MHz), audio (44.1/48 kHz), and display (up to 90 MHz pixel clock), with dedicated internal oscillators (64 MHz HSI, 4 MHz CSI, 32 kHz LSI) and external crystal support (8–48 MHz HSE, 32.768 kHz LSE).

Key Specifications

Pinout & Package

LFBGA289 (14 × 14 mm, 0.8 mm pitch) package with 289 I/O balls, ECOPACK2 compliant. Ball map defined per DS13483 Rev 7 Section 4 (Pinout, pin description and alternate functions), including dedicated VDD/VSS groups, DDR signal banks, and TrustZone-secured GPIO banks.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core Arm application processor applications.

Compared with NXP i.MX 8M Mini and Renesas RZ/G2L, the STM32MP135FAF7T uniquely combines TrustZone®-enforced peripheral security, dual CAN FD, integrated LCD-TFT, and hardware-accelerated crypto in a single LFBGA289 package-reducing BOM count and board area for space-constrained industrial HMI and gateway designs.

Availability

STM32MP135FAF7T is available at Aetrix Electronics and suitable for industrial HMI, edge gateways, smart camera nodes, and secure PLC modules requiring stable component supply across extended product lifecycles.

Supply support for STM32MP135FAF7T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader specializing in microcontrollers, power management, sensors, and automotive-grade processors with vertical manufacturing capability and ISO/TS 16949 certification.

The STM32MP series targets Linux-capable embedded applications demanding real-time responsiveness, hardware security, and rich peripheral integration-designed specifically for industrial automation, building control, and intelligent edge devices.

FAQ

What boot sources does the STM32MP135FAF7T support?

The STM32MP135FAF7T supports primary boot from eMMC, SD card, Quad-SPI NOR flash, and NAND flash via its flexible boot ROM. Boot mode is selected using BOOT0/BOOT1 pins, and secondary boot can be configured through the TF-A (Trusted Firmware-A) stage for secure firmware updates and fallback recovery paths.

Does the STM32MP135FAF7T include hardware support for real-time Linux determinism?

Yes-it integrates dual Cortex-A7 cores with ARM Generic Timer, secure RTC, and four independent system timers (secure/non-secure/virtual/hypervisor). Combined with TrustZone®-isolated peripherals and low-latency interrupt routing, it enables sub-10 µs interrupt response in PREEMPT_RT Linux configurations for motion control and industrial I/O.

How is DDR memory protected in secure applications?

DDR memory protection is enforced by the TrustZone Address Space Controller (TZC), which defines secure/non-secure memory regions and enforces access permissions at the AXI interconnect level. Combined with on-the-fly AES-128 DRAM encryption, this prevents DMA-based side-channel attacks and unauthorized memory snooping in multi-tenant environments.

What is the maximum camera resolution and frame rate supported?

The STM32MP135FAF7T supports up to 3 Mpix @30 fps in color or monochrome via its 8–16-bit parallel camera interface with 120 MHz pixel clock. For higher resolutions, it enables 5 Mpix @15 fps - sufficient for OCR, barcode scanning, and basic machine vision tasks without external FPGA preprocessing.