STMicroelectronics STM32MP135FAG7
- Part No.:
- STM32MP135FAG7
- Manufacturer:
- STMicroelectronics
- Category:
- Microprocessors
- Package:
- -
- Datasheet:
-
STM32MP135FAG7.pdf
- Description:
- 32-BIT ARM CORTEX-A7 900MHZ MPU
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Inventory:130
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Product details
Overview
STM32MP135FAG7 from STMicroelectronics is a dual-core Arm® Cortex®-A7 microprocessor operating up to 1 GHz, integrating LCD-TFT controller, dual CAN FD interfaces, dual 12-bit ADCs (5 Msps), and hardware crypto acceleration (AES-256, PKA, SHA-512). It supports LPDDR3-1066/DDR3L-1066 memory, features TrustZone® security, and targets industrial HMI, edge gateway, and secure IoT gateway applications.
For engineers reviewing the STM32MP135FAG7 datasheet, STM32MP135FAG7 pinout, STM32MP135FAG7 application, or STM32MP135FAG7 equivalent, key selection considerations include dual Cortex-A7 core timing alignment, DDR3/LPDDR3 memory interface compatibility, CAN FD protocol stack support, TrustZone® peripheral isolation configuration, and LTDC display bandwidth for WXGA@60fps.
Technical Context
The device implements a dual-core Arm Cortex-A7 subsystem with 128 KB unified L2 cache, NEON™ SIMD extension, and TrustZone® for secure world/non-secure world partitioning. Memory architecture includes 168 KB on-chip SRAM (128 KB AXI SYSRAM + 32 KB AHB SRAM + 8 KB backup SRAM) and external DDR controller supporting 16-bit LPDDR3-1066 or DDR3L-1066.
Peripherals are managed via dual interconnect matrices: a 64-bit AXI bus matrix (266 MHz) for high-bandwidth paths (DDR, GPU, LTDC) and a 32-bit AHB matrix (209 MHz) for low-latency peripherals (ADC, timers, I2C). Security is enforced by ETZPC, TZC, BSEC, and 12 tamper pins including 5 active tampers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Dual Arm Cortex-A7 @ up to 1 GHz with NEON and TrustZone |
| Memory Interface | 16-bit DDR3/DDR3L/LPDDR2/LPDDR3 up to 1066 MT/s; supports 1 Gbyte external SDRAM |
| On-chip SRAM | 168 Kbytes total: 128 KB AXI SYSRAM + 32 KB AHB SRAM + 8 KB Backup domain SRAM |
| Graphics | LCD-TFT controller supporting WXGA (1366×768) @ 60 fps or Full HD (1920×1080) @ 30 fps |
| Analog | 2 × 12-bit ADCs up to 5 Msps; 1 × temperature sensor; 1 × DFSDM with 4 channels |
| Security | Secure boot, TrustZone peripherals, AES-128/192/256, PKA (ECC/RSA), SHA-2/3, TRNG, 3072-bit fuses |
| Connectivity | 2 × CAN FD, 2 × Ethernet MAC/GMAC (IEEE 1588v2), 2 × USB 2.0 HS Host/OTG, 8–16-bit camera interface |
Pinout & Package
LFBGA289 package (14 × 14 mm, 0.8 mm pitch), RoHS-compliant and ECOPACK2 certified. Ball count: 289; thermal pad exposed on underside.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDCORE | Core power supply | 1.0 V ±5% supply for CPU and logic; requires low-noise regulation |
| VDDCPU | CPU voltage domain | Separate 1.0 V supply for Cortex-A7 cores; enables dynamic voltage scaling |
| VDDQ_DDR | DDR I/O power | 1.2 V or 1.35 V supply for DDR data/address bus; matches LPDDR3/DDR3L specs |
| NRST | Active-low reset input | Asynchronous reset pin with internal pull-up; triggers full system reset sequence |
| BOOT0 | Boot mode selection | Configures primary boot source (eMMC, SD, SPI NOR, NAND) at power-on |
| OSC_IN / OSC_OUT | HSE oscillator connection | 8–48 MHz crystal interface for system clock reference; supports analog/digital bypass modes |
Key Features
| Feature | Design Value |
|---|---|
| TrustZone-enabled peripheral isolation | Hardware-enforced separation of secure/non-secure peripherals via ETZPC and TZC |
| On-the-fly DRAM encryption | AES-128 encryption/decryption of DDR traffic in real time without CPU overhead |
| Dual independent watchdogs (IWDG1/IWDG2) | Redundant fail-safe monitoring: one for secure world, one for non-secure world |
| Flexible memory controller (FMC) | Supports SLC NAND with up to 8-bit ECC and parallel interface to external ASICs or FPGAs |
| MDMA controller | High-speed master DMA offloading CPU for memory-to-memory and peripheral transfers |
Applications
| Industrial HMI Panel | Secure Edge Gateway |
|---|---|
Use Scenario: Touchscreen-based control panel in factory automation with local data logging and remote diagnostics. IC Role / Device Role / Timing Role: Main application processor running Linux with real-time UI rendering via LTDC and touch input via I2C. Use Value: WXGA@60fps display output and dual CAN FD enable deterministic fieldbus communication while maintaining secure firmware updates via TrustZone. | Use Scenario: Protocol-agnostic industrial gateway aggregating Modbus, CAN FD, and Ethernet data for cloud upload. IC Role / Device Role / Timing Role: Dual Cortex-A7 handles concurrent network stacks (TCP/IP, MQTT) and fieldbus protocol translation with hardware-accelerated crypto. Use Value: AES-256 and PKA accelerate TLS 1.3 handshake and certificate validation; dual Ethernet MACs support redundant LAN links. |
| Smart Building Controller | Medical Imaging Edge Node |
Use Scenario: HVAC and lighting controller with local AI inference and secure OTA updates over cellular/Wi-Fi. IC Role / Device Role / Timing Role: Runs lightweight Linux distribution with secure boot chain and isolated secure storage for keys and certificates. Use Value: 3072-bit eFuses store HUK and unique ID; tamper detection disables sensitive functions upon physical intrusion attempt. | Use Scenario: Portable ultrasound or endoscopy device requiring real-time image processing and DICOM export. IC Role / Device Role / Timing Role: Processes raw sensor data from 8–16-bit camera interface and renders grayscale video via LTDC to embedded display. Use Value: 120 MHz pixel clock and dual-layer LTDC support overlay of UI elements on medical imagery with hardware alpha blending. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core Arm Cortex-A7 microprocessor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32MP157C-DK2 | Same dual Cortex-A7 core, but higher L2 cache (256 KB vs. 128 KB); lacks integrated DFSDM and has different ADC resolution (14-bit vs. 12-bit) | Targeted at higher-performance UI and multimedia; less optimized for sigma-delta sensor interfacing | Select when higher cache bandwidth and 14-bit ADC precision are required over DFSDM channel count |
| i.MX 8M Mini (NXP) | Quad Cortex-A53 + Cortex-M4; no TrustZone-peripheral controller; uses CAAM crypto block instead of SAES/PKA | Better suited for multi-threaded media pipelines; lacks ST's tamper-pin-based physical security architecture | Select when heterogeneous compute (A53+M4) and multimedia codec support outweigh need for active tamper response |
Compared with STM32MP135FAG7, STM32MP157C-DK2 offers greater L2 cache and ADC resolution but omits DFSDM-critical for delta-sigma sensor systems-while i.MX 8M Mini provides quad-A53 throughput and M4 co-processing at the cost of ST's fine-grained TrustZone peripheral isolation and 5 active tamper pins.
Availability
STM32MP135FAG7 is available at Aetrix Electronics and suitable for industrial HMI, secure edge gateways, smart building controllers, and medical imaging edge nodes requiring stable component supply across long-lifecycle deployments.
Supply support for STM32MP135FAG7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, designing and manufacturing microcontrollers, power ICs, sensors, and automotive-grade processors.
The STM32MP series targets Linux-capable, security-critical embedded applications where real-time responsiveness, hardware-enforced isolation, and long-term industrial support are mandatory.
FAQ
What boot sources does STM32MP135FAG7 support?
STM32MP135FAG7 supports boot from eMMC, SD card, SPI NOR flash, NAND flash (with BCH ECC), and UART via serial downloader. Boot mode is selected using BOOT0 and BOOT1 pins at power-on reset, with configuration stored in OTP memory for persistent fallback behavior.
Does STM32MP135FAG7 include hardware JPEG or video codec acceleration?
No. STM32MP135FAG7 does not integrate dedicated JPEG encode/decode or H.264/H.265 video codec hardware. Image processing relies on Cortex-A7 NEON instructions and software libraries; video streaming must be handled via external encoder or software-based solutions.
What is the maximum DDR clock frequency supported by STM32MP135FAG7?
The DDR controller supports up to 533 MHz data rate (1066 MT/s), compatible with LPDDR3-1066 and DDR3L-1066 standards. This requires precise PCB layout adherence to JEDEC timing budgets and proper termination for 16-bit data bus operation.
How is TrustZone security implemented beyond the CPU level?
TrustZone extends beyond CPU cores via ETZPC (external peripheral protection), TZC (DDR address space filtering), and BSEC (secure OTP and key management). Peripherals like ADC, timers, and I2C can be statically assigned to secure or non-secure worlds, and DDR accesses are filtered per-world basis to prevent unauthorized memory access.
STM32MP135FAG7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- -
- Series:
- -
- Packaging:
- Tray
- Product Status:
- Active
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- Ethernet:
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- Operating Temperature:
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- Additional Interfaces:
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STM32MP135FAG7 FAQ
1.How can I place an order for STM32MP135FAG7 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32MP135FAG7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32MP135FAG7 reliable?
The price and inventory of STM32MP135FAG7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32MP135FAG7 is usually 5 days.
3.What payment methods are accepted for STM32MP135FAG7?
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4.How is shipping managed for STM32MP135FAG7?
STM32MP135FAG7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32MP135FAG7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32MP135FAG7?
For technical support, including STM32MP135FAG7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32MP135FAG7 requirements.
6.How does Aetrix verify that STM32MP135FAG7 is sourced from the original manufacturer or authorized distributors?
All STM32MP135FAG7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32MP135FAG7 meets industry standards.
7.What is the process for return or replacement of STM32MP135FAG7?
All STM32MP135FAG7 units undergo pre-shipment inspection (PSI). If there is an issue with STM32MP135FAG7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32MP135FAG7 part is unused and in its original packaging.
Return procedure for STM32MP135FAG7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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