STMicroelectronics STM32MP151AAB3

Overview

STM32MP151AAB3 from STMicroelectronics is a dual-core heterogeneous microprocessor unit (MPU) integrating an Arm® Cortex®-A7 application core (800 MHz) and an Arm® Cortex®-M4 real-time core (209 MHz), with TrustZone® security, 708 KB on-chip SRAM, LPDDR2/LPDDR3/DDR3 memory support, and TFT LCD controller for embedded HMI applications in industrial gateways and smart displays.

For engineers reviewing the STM32MP151AAB3 datasheet, STM32MP151AAB3 pinout, STM32MP151AAB3 application, or STM32MP151AAB3 equivalent, key selection considerations include dual-core Linux + RTOS coexistence capability, 35 communication interfaces (including USB 2.0 HS Host/OTG, Gigabit Ethernet GMAC, HDMI-CEC), hardware crypto acceleration (SHA256/HMAC/RNG), and TFBGA361 (12 × 12 mm, 0.5 mm pitch) package compatibility with board-level thermal and signal integrity constraints.

Technical Context

The device implements a heterogeneous architecture where the Cortex-A7 subsystem runs Linux-based application stacks with AXI/AHB interconnects (266 MHz / 209 MHz), while the Cortex-M4 handles deterministic real-time tasks via shared memory and IPCC messaging. TrustZone® enforces secure world/non-secure world isolation at both CPU and peripheral levels.

Its memory subsystem includes 256 KB AXI SYSRAM, 384 KB AHB SRAM, and 64 KB backup-domain SRAM - all accessible with configurable cacheability and barrier control. The DDR controller supports LPDDR3-1066 (32-bit) and DDR3L-1066 (32-bit), enabling up to 1 Gbyte external memory with hardware ECC for NAND and SLC flash interfacing via FMC.

Key Specifications

Pinout & Package

STM32MP151AAB3 uses a TFBGA361 package (12 × 12 mm, 0.5 mm ball pitch, B031 variant), RoHS-compliant and ECOPACK2 certified. Ball mapping follows ST's standard STM32MP15x pinout layout with dedicated power domains (VDDCORE, VDD, VDDIO, VSS), multiple supply rails for analog/digital isolation, and configurable I/O banks supporting 5 V-tolerant operation on select pins.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core MPU applications.

Compared with i.MX 8M Mini and RZ/G2L, STM32MP151AAB3 uniquely combines TFT controller, TrustZone® peripheral isolation, and 5 V-tolerant I/Os in a compact TFBGA361 - making it optimal for cost-sensitive, display-integrated industrial controllers requiring hardware-rooted security.

Availability

STM32MP151AAB3 is available at Aetrix Electronics and suitable for industrial HMIs, smart building controllers, medical edge terminals, and automotive infotainment prototypes requiring stable component supply across extended product lifecycles.

Supply support for STM32MP151AAB3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and analog/mixed-signal devices for industrial, automotive, and consumer markets.

The STM32MP series targets heterogeneous computing in resource-constrained edge devices, combining Linux-capable application processing with real-time determinism and hardware security - specifically engineered for industrial IoT gateways and human-machine interfaces.

FAQ

What boot sources does STM32MP151AAB3 support?

STM32MP151AAB3 supports eight boot modes selected via BOOT0 and BOOT1 pins: eMMC, SD card, SPI NOR flash, Quad-SPI flash, NAND flash (via FMC), USB device (DFU mode), UART (for serial download), and internal ROM fallback. Each mode includes built-in first-stage bootloader (FSBL) validation and secure boot chain enforcement using OTP keys stored in BSEC.

Does STM32MP151AAB3 require an external PMIC?

No - STM32MP151AAB3 integrates multiple on-die LDOs (1.1 V for core, 1.8 V for USB PHY, 1.8 V for USB, ~0.9 V backup regulator) and supports direct connection to single 3.3 V or 5 V input. However, ST recommends using the STPMIC1 companion PMIC for full power sequencing, dynamic voltage scaling, and enhanced thermal management in production systems.

How is TrustZone® implemented on this device?

TrustZone® is implemented at three levels: CPU (secure/non-secure state partitioning), memory (TZC-400 controller for DDR address space protection), and peripherals (ETZPC controller assigning secure/non-secure access rights per peripheral). Secure world firmware (TF-A/OP-TEE) runs exclusively on Cortex-A7 in secure state, while Cortex-M4 operates in a physically isolated secure domain with dedicated SRAM and interrupts.

What is the maximum pixel clock frequency supported by the LTDC?

The LTDC supports a maximum pixel clock of 90 MHz, enabling WXGA (1366 × 768) at 60 fps or Full HD (1920 × 1080) at 30 fps with RGB888 color depth. This is achieved using the internal PLL generating precise pixel timing - no external clock generator required. Frame buffer memory must reside in AXI SYSRAM or DDR for optimal bandwidth.