STMicroelectronics STM32MP151AAD3T

Overview

STM32MP151AAD3T from STMicroelectronics is a dual-core Arm® Cortex®-A7 (800 MHz) + Cortex®-M4 (209 MHz) microprocessor unit with TrustZone® security, 708 KB on-chip SRAM, LPDDR2/LPDDR3/DDR3 memory controller, and integrated LCD-TFT controller supporting WXGA@60 fps. It delivers heterogeneous processing for Linux-capable edge nodes in industrial HMIs and smart gateways.

For engineers reviewing the STM32MP151AAD3T datasheet, STM32MP151AAD3T pinout, STM32MP151AAD3T application, or STM32MP151AAD3T equivalent, key selection criteria include dual-core boot partitioning, DDR memory retention in Standby mode (2 µA), TrustZone-enabled peripheral isolation, and hardware-accelerated crypto (SHA256/HMAC/RNG).

Technical Context

The device implements a split-world architecture: Cortex-A7 runs Linux-based applications with AMBA AXI/AHB interconnects (266 MHz / 209 MHz), while Cortex-M4 handles real-time control via dedicated DMA and low-power timers. Memory coherency is managed through hardware semaphore (HSEM) and inter-processor communication controller (IPCC).

Security is enforced at silicon level via TrustZone address space controller (TZC) for DDR, embedded tamper detection, active tamper pins, and BSEC-managed one-time programmable fuses (3072-bit, including 96-bit UID). Boot flow supports secure firmware update with hash verification and encrypted image loading.

Key Specifications

Pinout & Package

STM32MP151AAD3T uses a TFBGA361 (12 × 12 mm, 0.5 mm pitch) package compliant with ECOPACK2 environmental standards. Pin assignment follows ST's standardized ball map for STM32MP15x series, with dedicated power domains (VDDCORE, VDDIO, VDDUSB, VDDA), TrustZone-secured GPIOs (up to 8), and dedicated DDR interface lanes (DQ[15:0], DQS[1:0], CK/CK#, CKE, CS#, RAS#, CAS#, WE#).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core MPU applications.

Compared with i.MX 8M Mini and RZ/G2L, STM32MP151AAD3T uniquely balances ultra-low Standby power (2 µA), integrated TFT controller, and hardware-enforced TrustZone peripheral protection - making it optimal for battery-assisted, display-intensive, and security-certifiable industrial edge devices.

Availability

STM32MP151AAD3T is available at Aetrix Electronics and suitable for industrial HMIs, smart energy gateways, medical edge analyzers, and building automation controllers requiring stable component supply across extended product lifecycles.

Supply support for STM32MP151AAD3T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, MEMS, and automotive semiconductors since 1987.

The STM32MP series targets heterogeneous computing at the intelligent edge, combining Linux-capable application processing with real-time control and hardware security - specifically engineered for industrial IoT, human-machine interfaces, and secure gateway applications.

FAQ

What boot sources does STM32MP151AAD3T support?

STM32MP151AAD3T supports boot from eMMC, SD card, Quad-SPI NOR flash, and NAND flash via its flexible boot ROM. Boot mode is selected using BOOT0 and BOOT1 pins at power-on reset, with fallback to serial download mode via USB DFU if primary media fails. The BSEC block enforces secure boot chain verification before loading first-stage bootloader (FSBL).

Does STM32MP151AAD3T require an external PMIC?

No - STM32MP151AAD3T integrates multiple on-die LDOs (1.1 V core, 1.8 V USB, 1.8 V RETRAM, 0.9 V backup regulator) and supports direct connection to single 3.3 V supply. However, for high-current applications (>500 mA system load), ST recommends pairing with STPMIC1 to manage sequencing, dynamic voltage scaling, and thermal monitoring per ST's AN5138 application note.

How is TrustZone implemented on this MPU?

TrustZone is implemented at three levels: (1) Cortex-A7 core-level memory protection via TZASC for DDR, (2) ETZPC peripheral-level access control enforcing secure/non-secure register access, and (3) BSEC-managed secure boot and OTP key storage. Secure world execution is isolated via separate vector tables, memory maps, and interrupt routing - verified by ST's SBSFU reference implementation and certified to PSA Certified Level 2.

What is the maximum resolution and frame rate supported by the LTDC?

The LTDC supports up to WXGA (1366 × 768) at 60 fps or Full HD (1920 × 1080) at 30 fps with 24-bit RGB888 output and pixel clock up to 90 MHz. It includes dual-layer composition with alpha blending, programmable color LUT for gamma correction, and hardware cursor overlay - all without external video buffer or timing controller.