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STMicroelectronics STM32MP151CAC3
- Part No.:
- STM32MP151CAC3
- Manufacturer:
- STMicroelectronics
- Category:
- Microprocessors
- Package:
- 361-TFBGA
- Datasheet:
-
STM32MP151CAC3.pdf
- Description:
- IC MPU STM32MP1 650MHZ 361TFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:3,045
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Product details
Overview
STM32MP151CAC3 from STMicroelectronics is a dual-core Arm® Cortex®-A7 (800 MHz) + Cortex®-M4 (209 MHz) microprocessor unit with TrustZone® security, 708 KB on-chip SRAM, LPDDR2/LPDDR3/DDR3 memory support up to 1 Gbyte, and integrated LCD-TFT controller supporting WXGA@60 fps. It delivers heterogeneous processing for Linux-capable edge nodes with real-time control via the M4 core.
For engineers reviewing the STM32MP151CAC3 datasheet, STM32MP151CAC3 pinout, STM32MP151CAC3 application, or STM32MP151CAC3 equivalent, key selection considerations include dual-core asymmetric architecture, DDR memory interface timing compliance, TrustZone® peripheral isolation, and TFBGA361 (12 × 12 mm, 0.5 mm pitch) mechanical compatibility in industrial HMI and gateway designs.
Technical Context
The device implements a split-domain interconnect: a 64-bit AXI bus matrix (266 MHz) for high-bandwidth A7 subsystem access to DDR, GPU, and peripherals, and a 32-bit AHB matrix (209 MHz) for M4 and low-latency peripherals. Memory coherency is maintained via hardware snoop control unit (SCU) and cache-enabled interconnect.
Security is enforced at silicon level through TrustZone® address space controller (TZC) for DDR, embedded TrustZone protection controller (ETZPC), secure boot with BSEC OTP fuses, and isolated M4 execution environment-enabling secure firmware updates, encrypted storage, and tamper-resistant runtime partitioning.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: Arm® Cortex®-A7 @ 800 MHz + Cortex®-M4 @ 209 MHz - enables Linux OS on A7 with deterministic real-time tasks on M4 |
| On-chip SRAM | 708 KB total: 256 KB AXI SYSRAM + 384 KB AHB SRAM + 64 KB Backup SRAM + 4 KB Backup domain SRAM - supports multi-context RTOS and secure boot stacks |
| External Memory Support | LPDDR2/LPDDR3-1066 or DDR3/DDR3L-1066, 16/32-bit bus - enables cost-optimized 512 MB–1 GB DDR solutions with <10 ns tAC timing margin |
| Graphics Interface | LCD-TFT controller with 24-bit RGB888, pixel clock up to 90 MHz - drives WXGA (1366×768) @60 fps or Full HD (1920×1080) @30 fps displays directly |
| Crypto Acceleration | AES-128/192/256, TDES, SHA-1/224/256, HMAC, two TRNGs - offloads TLS 1.2/1.3 handshake and secure OTA update verification |
| Package | TFBGA361, 12 × 12 mm, 0.5 mm ball pitch, ECOPACK2-compliant - compatible with standard PCB assembly processes and thermal vias under die |
| Power Modes | Standby mode draws 2 µA (no RTC, no LSE, no BKPSRAM, no RETRAM) - enables battery-backed wake-on-event operation for remote sensors |
Pinout & Package
TFBGA361 package (ball pitch: 0.5 mm, dimensions: 12 × 12 mm, 361 I/O balls). Pinout validated per STMicroelectronics DS12501 Rev 9, Section 4 ("Pinouts, pin description and alternate functions") and Package Info B031.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDCORE | Core power supply | 1.1 V ±3% regulated input for Cortex-A7/M4 cores and L1/L2 caches - requires low-noise 10 µF ceramic decoupling |
| VDDIO_1 | I/O bank 1 supply | 1.71–3.6 V tolerant supply for GPIOs, UART, SPI, I2C - enables direct interfacing with 3.3 V or 1.8 V peripherals |
| NRST | System reset input | Active-low asynchronous reset for entire SoC - must be held low ≥20 µs after power stabilization per POR sequence |
| BOOT0 | Boot mode selection | High at power-up selects internal Flash or eMMC boot; low selects SD card or USB DFU - determines initial vector fetch location |
| CLKIN | External clock input | Accepts 8–48 MHz crystal or oscillator for HSE - feeds PLLs generating CPU, AXI, and peripheral clocks with <±50 ppm stability |
| ETH_MDIO | GMAC management data I/O | Open-drain bidirectional interface for PHY register access - operates at ≤2.5 MHz, requires 1.5 kΩ pull-up to VDDIO |
Key Features
| Feature | Design Value |
|---|---|
| Arm® TrustZone® Security | Hardware-enforced isolation between secure/non-secure worlds, including TZC-controlled DDR access and ETZPC-peripheral gating |
| Dual-Mode Quad-SPI Interface | Supports XIP (execute-in-place) and memory-mapped mode for external flash - reduces boot time by eliminating copy-to-RAM overhead |
| Advanced Timer Set | 2 × 32-bit timers with quadrature encoder input + 2 × 16-bit advanced motor control timers - enables closed-loop servo drive without external FPGA |
| Audio Subsystem | 4 × SAI interfaces + SPDIF RX (4-channel) + internal audio PLL - supports multi-zone audio playback and HDMI-CEC synchronized volume control |
| Camera Interface | DCMI with 8–14-bit parallel input, up to 140 MB/s throughput - captures 1080p30 video directly into DDR without frame buffer bottlenecks |
Applications
| Industrial HMI Panel | Smart Gateway Controller |
|---|---|
Use Scenario: Touch-enabled factory floor display with real-time PLC status visualization and local alarm logging. IC Role / Device Role / Timing Role: MPU executes Qt-based Linux GUI on Cortex-A7 while Cortex-M4 handles CANopen slave stack and analog sensor polling at 1 kHz. Use Value: Dual-core separation eliminates Linux jitter from real-time I/O servicing; TFT controller drives 7-inch WVGA display at 60 fps without GPU acceleration. | Use Scenario: Edge node aggregating Modbus RTU, BLE, and LoRaWAN traffic before forwarding to cloud via Ethernet or USB host. IC Role / Device Role / Timing Role: Cortex-A7 runs OpenWrt router stack and TLS-secured MQTT client; Cortex-M4 manages low-power radio state machines and packet framing. Use Value: Integrated GMAC with IEEE 1588v2 hardware timestamping enables sub-microsecond time synchronization across distributed sensors. |
| Medical Diagnostic Terminal | Automotive Infotainment Prototype |
Use Scenario: Portable ultrasound preview station with live image rendering, touch UI, and DICOM export over USB. IC Role / Device Role / Timing Role: Cortex-A7 hosts Linux-based imaging software and USB mass storage class; Cortex-M4 acquires ADC samples from transducer front-end at 4.5 Msps. Use Value: 16-bit ADC with hardware oversampling and DFSDM sigma-delta filtering achieves >90 dB SNR for analog signal conditioning without external precision ADC. | Use Scenario: In-vehicle rear-seat entertainment unit with HDMI output, stereo audio playback, and vehicle bus monitoring. IC Role / Device Role / Timing Role: Cortex-A7 renders Android Automotive UI and decodes HDMI-CEC commands; Cortex-M4 monitors LIN bus diagnostics and controls backlight dimming PWM. Use Value: Integrated HDMI-CEC controller and SAI/I2S audio interfaces eliminate discrete transceivers, reducing BOM count and EMI risk in EMC-sensitive automotive environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core MPU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| i.MX 8M Mini (NXP) | Quad-core Cortex-A53 + Cortex-M4, no TrustZone®-enabled DDR controller; uses external PMIC for all rails | Requires external DDR PHY tuning and separate secure boot ROM; lacks integrated LDOs for USB/1.8 V domains | Preferred when higher A-class compute (A53 vs A7) and MIPI-CSI2 camera interface are required over TrustZone® memory firewalling |
| RZ/G2L (Renesas) | Dual-core Cortex-A55 + Cortex-M33, 2 GB LPDDR4 support, no integrated TFT controller or DCMI | Relies on external display bridge IC; lacks hardware-accelerated crypto engines (AES/SHA only in software) | Chosen for longer product lifecycle commitment and ASIL-B functional safety certification path, not for display-integrated edge nodes |
Compared with i.MX 8M Mini and RZ/G2L, STM32MP151CAC3 uniquely integrates TrustZone®-protected DDR access, on-die LDOs for USB and backup domains, and a full-featured TFT controller - making it optimal for cost-sensitive, display-centric industrial gateways requiring hardware-enforced security boundaries.
Availability
STM32MP151CAC3 is available at Aetrix Electronics and suitable for industrial HMI, smart gateway, medical diagnostic terminal, and automotive infotainment prototype applications requiring stable component supply across extended product lifecycles.
Supply support for STM32MP151CAC3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and analog/mixed-signal devices for industrial, automotive, and consumer markets.
The STM32MP series targets heterogeneous computing in resource-constrained edge devices, combining Linux-capable application cores with real-time microcontroller subsystems - specifically engineered for secure, display-rich industrial and IoT endpoints.
FAQ
What boot sources does STM32MP151CAC3 support?
STM32MP151CAC3 supports boot from eMMC, SD card, NAND flash, Quad-SPI NOR flash, USB device (DFU mode), and UART (for serial download). Boot mode is selected via BOOT0 and BOOT1 pins at power-up, with configuration stored in BSEC OTP fuses for permanent fallback behavior.
Does STM32MP151CAC3 require an external PMIC?
No - STM32MP151CAC3 integrates multiple on-die LDOs: 1.1 V for core, 1.8 V for USB PHY, 1.8 V for USB logic, and ~0.9 V backup regulator. An external PMIC is optional for system-level power sequencing or high-efficiency buck conversion but not mandatory for basic operation.
How is TrustZone® implemented in this MPU?
TrustZone® is implemented via hardware blocks: TrustZone Address Space Controller (TZC) enforces memory access permissions on DDR, Embedded TrustZone Protection Controller (ETZPC) gates peripheral access, and Secure Monitor Call (SMC) instructions manage world switches. All secure peripherals (RNG, CRYP, HASH) reside in the secure world and are inaccessible from non-secure software without explicit SMC calls.
What is the maximum resolution supported by the integrated LCD-TFT controller?
The LTDC controller supports up to WXGA (1366 × 768) at 60 fps or Full HD (1920 × 1080) at 30 fps, with pixel clock up to 90 MHz and dual-layer composition with programmable color LUT. It accepts RGB666, RGB888, and YUV422 inputs and supports active matrix TFT panels with LVDS or RGB interface.
STM32MP151CAC3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 361-TFBGA
- Series:
- STM32MP1
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A7
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 209MHz, 650MHz
- Co-Processors/DSP:
- ARM® Cortex®-M4
- RAM Controllers:
- DDR3, DDR3L, LPDDR2, LPDDR3
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- HDMI-CEC, LCD
- Ethernet:
- 10/100Mbps, GbE
- SATA:
- -
- USB:
- USB 2.0 (2), USB 2.0 OTG+ PHY (3)
- Voltage - I/O:
- 2.5V, 3.3V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- ARM TZ
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 361-TFBGA (12x12)
- Additional Interfaces:
- CAN, Ethernet, I2C, MMC/SD/SDIO, SPDIF, SPI, UART, USB
STM32MP151CAC3 FAQ
1.How can I place an order for STM32MP151CAC3 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32MP151CAC3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32MP151CAC3 reliable?
The price and inventory of STM32MP151CAC3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32MP151CAC3 is usually 5 days.
3.What payment methods are accepted for STM32MP151CAC3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32MP151CAC3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32MP151CAC3?
STM32MP151CAC3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32MP151CAC3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32MP151CAC3?
For technical support, including STM32MP151CAC3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32MP151CAC3 requirements.
6.How does Aetrix verify that STM32MP151CAC3 is sourced from the original manufacturer or authorized distributors?
All STM32MP151CAC3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32MP151CAC3 meets industry standards.
7.What is the process for return or replacement of STM32MP151CAC3?
All STM32MP151CAC3 units undergo pre-shipment inspection (PSI). If there is an issue with STM32MP151CAC3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32MP151CAC3 part is unused and in its original packaging.
Return procedure for STM32MP151CAC3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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