STMicroelectronics STM32MP153AAB3
- Part No.:
- STM32MP153AAB3
- Manufacturer:
- STMicroelectronics
- Category:
- Microprocessors
- Package:
- 354-LFBGA
- Datasheet:
-
STM32MP153AAB3.pdf
- Description:
- IC MPU STM32MP1 650MHZ 354LFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
STM32MP153AAB3 from STMicroelectronics is a dual-core Arm® Cortex®-A7 (800 MHz) + Cortex®-M4 microprocessor unit (MPU) with TrustZone®, NEON™, and integrated TFT LCD controller. It delivers 29 timers, 37 communication interfaces (including 2× CAN FD, Gigabit Ethernet, USB 2.0 HS Host/OTG), and advanced analog peripherals (2× 16-bit ADCs, 2× 12-bit DACs). Designed for industrial HMI, edge gateway, and smart display applications requiring secure Linux-capable processing with real-time M4 co-processing.
For engineers reviewing the STM32MP153AAB3 datasheet, STM32MP153AAB3 pinout, STM32MP153AAB3 application, or STM32MP153AAB3 equivalent, key selection considerations include dual-core asymmetric architecture support, DDR3/LPDDR3 memory interface timing, TrustZone-enabled peripheral isolation, and TFBGA361 (12 × 12 mm, 0.5 mm pitch) mechanical compatibility in space-constrained embedded designs.
Technical Context
The device implements a heterogeneous dual-core architecture: two Cortex-A7 cores share a 256-Kbyte unified L2 cache and run at up to 800 MHz, while the Cortex-M4 operates at up to 209 MHz with FPU and MPU-enabling concurrent Linux-based application execution and deterministic real-time control. Memory subsystem includes 708 Kbytes of on-chip SRAM (AXI/AHB domains + backup SRAM) and external DDR3/LPDDR3-1066 support via dedicated controller.
Communication subsystem integrates 6× I²C FM+, 8× UART/USART (12.5 Mbit/s), 6× SPI (50 Mbit/s), 4× SAI, 2× CAN FD (one TTCAN), Gigabit Ethernet GMAC with IEEE 1588v2 hardware timestamping, and HDMI-CEC-enabling full-stack connectivity for industrial IoT gateways and multimedia HMI systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual Arm® Cortex®-A7 @ 800 MHz + single Cortex®-M4 @ 209 MHz - enables Linux + RTOS coexistence with hardware-isolated memory domains. |
| Memory Interface | LPDDR2/LPDDR3-1066 or DDR3/DDR3L-1066 (16/32-bit bus) - supports up to 1 Gbyte external DRAM for high-bandwidth GUI and video buffering. |
| Analog Peripherals | 2× 16-bit ADCs (up to 3.6 Msps), 2× 12-bit DACs (1 MHz), DFSDM with 8 channels - suitable for precision sensor acquisition and audio playback in industrial control panels. |
| Graphics Support | LCD-TFT controller supporting WXGA (1366×768@60 fps) or Full HD (1920×1080@30 fps) - enables rich GUI rendering without external GPU in cost-sensitive HMIs. |
| Security Features | Arm® TrustZone®, active tamper detection, 3072-bit fuses (96-bit unique ID), HASH (SHA256), 2× TRNG - meets IEC 62443-3-3 requirements for secure boot and firmware integrity. |
| Package | TFBGA361 (12 × 12 mm, 0.5 mm pitch) - RoHS-compliant ECOPACK2 package optimized for automated assembly and thermal performance in compact enclosures. |
| Power Modes | Standby mode current down to 2 µA (no RTC/LSE/BKPSRAM/RETRAM) - enables battery-backed operation for remote monitoring nodes with multi-year runtime. |
Pinout & Package
STM32MP153AAB3 uses a 361-ball TFBGA package (12 × 12 mm, 0.5 mm pitch), designated B031 per ST's package documentation. Ball mapping supports 176 GPIOs (including 8 secure I/Os), dual DDR3/LPDDR3 interfaces, and dedicated high-speed signal routing for USB HS, GMAC, and camera interface (DCMI).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDCORE | Core power supply | 1.1 V ±3% regulated input for Cortex-A7/M4 logic; requires low-noise decoupling due to dynamic current demands up to 1.2 A. |
| VDD_DDR | DDR memory I/O supply | 1.35 V (DDR3L) or 1.2 V (LPDDR2/LPDDR3); must be sequenced after VDDCORE and synchronized with DDR controller initialization. |
| NRST_CORE | Core reset input | Asynchronous active-low reset for Cortex-A7 subsystem only; independent of M4 domain reset for flexible recovery partitioning. |
| BOOT0 / BOOT1 | Boot mode selection | Two-pin strap configuration determining primary boot source (eMMC, SD card, NAND, QSPI, USB) - critical for field firmware update resilience. |
| ETH_MDIO / ETH_MDC | GMAC management interface | IEEE 802.3-compliant MDIO bus for PHY register access; supports auto-negotiation and link status monitoring in industrial Ethernet deployments. |
Key Features
| Feature | Design Value |
|---|---|
| Asymmetric Dual-Core Architecture | Enables simultaneous Linux OS execution on A7 cores and deterministic real-time control on M4 core-eliminating need for separate MCU in gateway/HMI designs. |
| TrustZone-Protected Peripheral Isolation | Hardware-enforced memory and peripheral access separation between secure/non-secure worlds-required for PSA Certified Level 1 compliance in connected devices. |
| Integrated LCD-TFT Controller | Supports RGB888 24-bit parallel output, dual-layer composition, and programmable color LUT-reduces BOM cost by removing external display bridge ICs. |
| Gigabit Ethernet with IEEE 1588v2 | Hardware timestamping engine enables sub-microsecond time synchronization for industrial automation protocols (e.g., TSN, PROFINET IRT). |
| Flexible Boot Options | Supports eMMC, SD, NAND Flash, Quad-SPI NOR, and USB mass storage-facilitates secure over-the-air updates and factory programming flexibility. |
Applications
| Industrial HMI Panel | Edge Gateway |
|---|---|
Use Scenario: Touchscreen operator interface for PLC-controlled machinery with local data logging and web-based diagnostics. IC Role / Device Role / Timing Role: Main application processor running embedded Linux (Yocto), driving 7-inch TFT display via LTDC, managing CAN FD fieldbus communication, and executing real-time motion control on Cortex-M4. Use Value: Eliminates dual-chip architecture by integrating GUI rendering, network stack, and deterministic control-reducing PCB area by 35% and system latency under 100 µs for servo loop closure. |
Use Scenario: Smart building controller aggregating Modbus RTU, BACnet MS/TP, and LoRaWAN sensor data before forwarding to cloud via TLS-secured MQTT over Gigabit Ethernet. IC Role / Device Role / Timing Role: Secure application host (A7) handling protocol translation and TLS encryption, with M4 offloading sensor fusion and watchdog supervision. Use Value: TrustZone isolates crypto keys and OTA update verification from application code-meeting UL 2900-1 cybersecurity validation requirements for commercial HVAC systems. |
| Medical Display Terminal | Automotive Infotainment Prototype |
Use Scenario: Portable ultrasound imaging console with real-time image processing, touch UI, and DICOM export over WiFi/Ethernet. IC Role / Device Role / Timing Role: A7 cores run Linux-based imaging software and network stack; M4 handles time-critical ADC sampling and beamforming pre-processing. Use Value: Dual 16-bit ADCs (4.5 Msps) and DFSDM enable direct sigma-delta sensor interfacing-reducing analog front-end component count and improving SNR by 12 dB versus discrete solutions. |
Use Scenario: In-vehicle infotainment development platform supporting Android Automotive OS, rear-seat entertainment, and CAN FD vehicle diagnostics. IC Role / Device Role / Timing Role: Primary SoC providing GPU-accelerated UI, dual-display output (HDMI + LVDS), and time-triggered CAN (TTCAN) for ECU communication testing. Use Value: TTCAN peripheral supports deterministic message scheduling aligned to system clock-enabling accurate simulation of automotive network timing constraints during validation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core MPU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXP i.MX 8M Mini (LPC55S69) | Quad-core Cortex-A53 + Cortex-M33; lacks TrustZone-peripheral isolation and integrated TFT controller; higher power envelope (2.5 W typical vs. 1.8 W). | Better suited for AI inference workloads but requires external display bridge and separate security IC for comparable PSA Level 1 compliance. | Select when ML acceleration (NNPU) is prioritized over display integration and ultra-low standby power. |
| Renesas RZ/G2L (R9A07G043L2) | Single Cortex-A55 + Cortex-M33; no dual-A7 symmetry; supports LPDDR4 but lacks CAN FD and HDMI-CEC; lower peripheral count (26 vs. 37 interfaces). | Targeted at entry-level Linux HMI with basic connectivity; insufficient for time-critical TTCAN or multi-gigabit Ethernet applications. | Select for cost-sensitive consumer displays where CAN FD and IEEE 1588 are not required. |
Compared with i.MX 8M Mini and RZ/G2L, STM32MP153AAB3 uniquely balances Linux application capability, real-time M4 co-processing, integrated graphics, and industrial-grade security-all within a 12×12 mm footprint and 2 µA standby current-making it optimal for space- and power-constrained edge devices requiring certified trust anchors.
Availability
STM32MP153AAB3 is available at Aetrix Electronics and suitable for industrial HMI, edge gateway, medical display terminal, and automotive infotainment prototype applications requiring stable component supply across multi-year production cycles.
Supply support for STM32MP153AAB3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog components for industrial, automotive, and consumer markets.
STM32MP series MPUs target Linux-capable embedded applications demanding security, graphics, and real-time responsiveness-bridging the gap between microcontrollers and application processors for intelligent edge devices.
FAQ
What boot sources does STM32MP153AAB3 support?
STM32MP153AAB3 supports boot from eMMC, SD card, NAND Flash, Quad-SPI NOR, USB mass storage, and internal ROM. Boot mode is selected via BOOT0/BOOT1 pins, and secondary boot sources (e.g., fallback to QSPI if eMMC fails) can be configured in the First Stage Boot Loader (FSBL) stored in OTP.
Does STM32MP153AAB3 require an external PMIC?
No-STM32MP153AAB3 integrates multiple on-chip LDOs (1.1 V, 1.8 V, 3.3 V) and a backup regulator (~0.9 V), enabling direct connection to single 3.3 V or 5 V input. However, external PMICs like STPMIC1 are recommended for high-efficiency multi-rail sequencing in battery-powered designs.
How is TrustZone implemented on this device?
TrustZone is implemented at both CPU and peripheral levels: Cortex-A7 cores enforce secure/non-secure world separation via TZASC (TrustZone Address Space Controller) for DDR, ETZPC (Embedded TrustZone Protection Controller) for peripheral access, and secure boot ROM enforcing authenticated firmware loading before non-secure code execution.
What is the maximum resolution supported by the LTDC controller?
The LTDC controller supports up to Full HD (1920 × 1080) at 30 fps or WXGA (1366 × 768) at 60 fps, with pixel clock up to 90 MHz. It features dual-layer composition, alpha blending, and programmable color LUT-enabling overlay graphics and dynamic theme switching without GPU acceleration.
STM32MP153AAB3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 354-LFBGA
- Series:
- STM32MP1
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A7
- Number of Cores/Bus Width:
- 2 Core, 32-Bit
- Speed:
- 209MHz, 650MHz
- Co-Processors/DSP:
- ARM® Cortex®-M4
- RAM Controllers:
- DDR3, DDR3L, LPDDR2, LPDDR3
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- HDMI-CEC, LCD
- Ethernet:
- 10/100Mbps (1)
- SATA:
- -
- USB:
- USB 2.0 (2), USB 2.0 OTG+ PHY (3)
- Voltage - I/O:
- 2.5V, 3.3V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- ARM TZ
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 354-LFBGA (16x16)
- Additional Interfaces:
- CAN, Ethernet, I2C, MMC/SD/SDIO, SPDIF, SPI, UART, USB
STM32MP153AAB3 FAQ
1.How can I place an order for STM32MP153AAB3 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32MP153AAB3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32MP153AAB3 reliable?
The price and inventory of STM32MP153AAB3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32MP153AAB3 is usually 5 days.
3.What payment methods are accepted for STM32MP153AAB3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32MP153AAB3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32MP153AAB3?
STM32MP153AAB3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32MP153AAB3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32MP153AAB3?
For technical support, including STM32MP153AAB3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32MP153AAB3 requirements.
6.How does Aetrix verify that STM32MP153AAB3 is sourced from the original manufacturer or authorized distributors?
All STM32MP153AAB3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32MP153AAB3 meets industry standards.
7.What is the process for return or replacement of STM32MP153AAB3?
All STM32MP153AAB3 units undergo pre-shipment inspection (PSI). If there is an issue with STM32MP153AAB3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32MP153AAB3 part is unused and in its original packaging.
Return procedure for STM32MP153AAB3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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