STMicroelectronics STM32MP153AAC3T
- Part No.:
- STM32MP153AAC3T
- Manufacturer:
- STMicroelectronics
- Category:
- Microprocessors
- Package:
- 361-TFBGA
- Datasheet:
-
STM32MP153AAC3T.pdf
- Description:
- IC MPU STM32MP1 650MHZ 361TFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:3,317
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32MP153AAC3T from STMicroelectronics is a dual-core Arm® Cortex®-A7 (800 MHz) + Cortex®-M4 microprocessor unit (MPU) with TrustZone®, NEON™, and integrated TFT LCD controller. It delivers 29 timers, 37 communication interfaces (including 2× CAN FD, Gigabit Ethernet, USB 2.0 HS Host/OTG), and advanced analog peripherals (2× 16-bit ADCs, 2× 12-bit DACs). It targets industrial HMI, edge gateway, and embedded vision systems requiring secure Linux execution and real-time control.
For engineers reviewing the STM32MP153AAC3T datasheet, STM32MP153AAC3T pinout, STM32MP153AAC3T application, or STM32MP153AAC3T equivalent, key selection considerations include dual-core isolation via TrustZone®, DDR3/LPDDR3 memory support up to 1 Gbyte, 176 I/Os with tamper detection, and hardware-accelerated crypto (SHA256, HMAC, RNG).
Technical Context
The device implements a heterogeneous dual-core architecture: two Cortex-A7 cores share a 256-Kbyte unified L2 cache and run Linux in secure/non-secure worlds, while the Cortex-M4 (209 MHz) handles deterministic real-time tasks with FPU and MPU. Inter-core communication uses IPCC and hardware semaphores (HSEM).
Clock management includes five fractional PLLs supporting precise domain-specific frequencies; memory subsystem integrates AXI (266 MHz) and AHB (209 MHz) interconnects, DDRCTRL with ECC, and dual-mode Quad-SPI for code/data execution. Security relies on TrustZone peripherals, active tamper detection, and BSEC OTP fuses.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual Arm Cortex-A7 @ 800 MHz + single Cortex-M4 @ 209 MHz - enables Linux + RTOS coexistence with hardware-isolated execution domains |
| Memory Interface | LPDDR2/LPDDR3-1066 or DDR3/DDR3L-1066 up to 1 Gbyte - supports high-bandwidth OS and application data with configurable 16/32-bit bus width |
| Internal SRAM | 708 Kbytes total: 256 KB AXI SYSRAM + 384 KB AHB SRAM + 64 KB Backup SRAM + 4 KB Backup SRAM - enables fast boot, context retention, and RTC-critical data storage |
| Analog Peripherals | 2× 16-bit ADCs (up to 3.6 Msps), 2× 12-bit DACs (1 MHz), DFSDM with 8 channels - supports precision sensor acquisition and audio signal generation |
| Communication Interfaces | 6× I2C, 8× UART/USART, 6× SPI, 4× SAI, 2× CAN FD (1× TTCAN), Gigabit Ethernet GMAC, 3× SDMMC - full-stack connectivity for industrial fieldbus, audio, storage, and time-sensitive networking |
| Graphics & Display | LCD-TFT controller supporting WXGA @60 fps or Full HD @30 fps with dual layers and programmable LUT - enables rich GUI rendering without external GPU |
| Security Features | Arm TrustZone, active tamper pins, 3072-bit fuses (96-bit UID), HASH (SHA256), 2× TRNG, BSEC OTP - provides hardware-rooted secure boot, firmware attestation, and runtime integrity |
Pinout & Package
STM32MP153AAC3T is packaged in a TFBGA361 (12 × 12 mm, 0.5 mm pitch) with 361 balls. The package complies with ECOPACK2 environmental standards and supports industrial temperature range (–40°C to +125°C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDCORE | Core power supply | 1.1 V regulated input for CPU and logic domains; requires low-noise filtering per datasheet Section 6.3.5 |
| VDDIO | I/O power supply | 1.71–3.6 V supply enabling 5 V-tolerant operation on most GPIOs; supports mixed-voltage system interfacing |
| NRST | System reset input | Active-low asynchronous reset controlling entire chip; monitored by embedded PDR/POR/BOR circuitry |
| BOOT0 | Boot mode selection | Configures primary boot source (eMMC, NAND, QSPI, SD card) at power-up; sampled during reset sequence |
| OSC_IN / OSC_OUT | External crystal oscillator interface | Supports 8–48 MHz HSE crystal for precise clock reference; required for USB/Ethernet timing compliance |
| ETH_MDIO / ETH_MDC | Ethernet management interface | Provides IEEE 802.3-compliant PHY configuration and status readback for GMAC peripheral |
| DCMI_D0–D7 / DCMI_HSYNC / VSYNC | Digital camera interface signals | 8-bit parallel interface supporting up to 140 Mbyte/s capture - enables direct connection to CMOS image sensors |
Key Features
| Feature | Design Value |
|---|---|
| TrustZone-enabled dual-core isolation | Hardware-enforced separation between Cortex-A7 secure world (Linux kernel) and non-secure world (user space), plus Cortex-M4 real-time domain |
| Hardware crypto acceleration | Dedicated HASH (MD5/SHA1/SHA224/SHA256) and HMAC engines reduce CPU load during TLS/OTA update operations |
| Flexible memory mapping | Quad-SPI dual-mode interface allows XIP (execute-in-place) from flash and seamless fallback to external SDRAM for large applications |
| Low-power standby with DDR retention | 2 µA current draw in Standby mode while preserving DDR contents - enables instant resume without full reinitialization |
| Advanced timer subsystem | 29 timers including 2× 32-bit general-purpose, 2× advanced motor control, 10× 16-bit GP, 5× LP timers, and RTC with sub-second accuracy - supports complex motion control and time-synchronized I/O |
Applications
| Industrial HMI Panel | Edge Gateway Device |
|---|---|
Use Scenario: Touchscreen-based operator interface for PLC-controlled machinery with local data logging and remote diagnostics. IC Role / Device Role / Timing Role: MPU executes Linux-based Qt GUI, manages TFT display via LTDC, processes serial fieldbus data (CAN FD, RS485 over USART), and runs secure OTA updates. Use Value: Dual-core architecture isolates GUI rendering (Cortex-A7) from real-time I/O handling (Cortex-M4), ensuring deterministic response to button presses and alarm triggers. | Use Scenario: Smart factory node aggregating sensor data from Modbus RTU devices and forwarding to cloud via TLS-secured MQTT over Ethernet/WiFi. IC Role / Device Role / Timing Role: Acts as protocol translator and security anchor: Cortex-A7 hosts EdgeX Foundry, GMAC handles IEEE 1588v2 time sync, TrustZone secures key storage and crypto operations. Use Value: Integrated Gigabit Ethernet with hardware timestamping and SHA256 acceleration enables low-latency, authenticated data transmission without external crypto ICs. |
| Embedded Vision System | Secure Digital Signage |
Use Scenario: Real-time object detection on conveyor belt using CMOS camera feed and lightweight neural network inference. IC Role / Device Role / Timing Role: DCMI captures 720p@30fps video; Cortex-M4 pre-processes frames; Cortex-A7 runs TensorFlow Lite Micro; LTDC drives HDMI-CEC display. Use Value: Parallel camera interface (140 MB/s) and dual-layer LCD controller eliminate frame buffering latency, enabling sub-100ms end-to-end processing. | Use Scenario: Public kiosk displaying encrypted advertising content with anti-tamper monitoring and remote content updates. IC Role / Device Role / Timing Role: MPU validates signed firmware images using BSEC OTP keys, renders graphics via LTDC, detects physical intrusion via active tamper pins, and logs events to secure eMMC. Use Value: Hardware-backed secure boot and active tamper detection prevent unauthorized firmware modification and physical tampering - meeting EN 50131 Grade 2 requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar MPU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXP i.MX 8M Mini (LPC55S69) | Quad Cortex-A53 + Cortex-M33; lacks integrated TFT controller and TrustZone-peripheral isolation; different DDR interface (LPDDR4 only) | Better multimedia codec support but no native LCD-TFT; requires external display bridge for RGB panels | Select when prioritizing video decode (H.265) over integrated display driving and deterministic real-time control |
| Renesas RZ/G2L (R9A07G043L2) | Dual Cortex-A55 + Cortex-M33; includes 3D GPU and MIPI-DSI; no CAN FD or active tamper; lower SRAM (512 KB) | Stronger graphics performance for Android-based UIs; weaker industrial I/O and security feature set | Select for consumer-facing displays needing OpenGL ES acceleration, not for safety-critical industrial control |
Compared with NXP i.MX 8M Mini and Renesas RZ/G2L, STM32MP153AAC3T uniquely combines TrustZone-peripheral security, integrated TFT-LCD controller, CAN FD with TTCAN, and 708 KB on-chip SRAM - making it optimal for cost-sensitive, Linux-based industrial HMIs requiring hardware-rooted security and deterministic real-time responsiveness.
Availability
STM32MP153AAC3T is available at Aetrix Electronics and suitable for industrial HMI, edge gateway, and embedded vision systems requiring stable component supply across extended product lifecycles.
Supply support for STM32MP153AAC3T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in microcontrollers, power management, sensors, and automotive ICs.
The STM32MP series targets heterogeneous computing for industrial and IoT edge devices, combining Linux-capable application processors with real-time microcontroller cores to unify high-level OS functionality and deterministic control in a single chip.
FAQ
What boot sources does STM32MP153AAC3T support?
STM32MP153AAC3T supports boot from eMMC, SLC NAND, Quad-SPI NOR/NAND, SD card, and USB mass storage via its flexible boot ROM. Boot mode is selected using BOOT0 and BOOT1 pins, and the first-stage bootloader (FSBL) validates signature before loading TF-A or U-Boot. External NOR flash with XIP capability enables fast cold-start execution.
Does STM32MP153AAC3T require an external PMIC?
No - STM32MP153AAC3T integrates multiple on-chip LDOs (1.1 V core, 1.8 V USB, 1.8 V RETRAM, 0.9 V backup) and a dedicated backup regulator. However, a companion PMIC like STPMIC1 is recommended for high-efficiency multi-rail power sequencing, thermal monitoring, and dynamic voltage scaling in production systems.
How is TrustZone implemented on this MPU?
TrustZone is implemented at both processor and peripheral levels: Cortex-A7 cores enforce secure/non-secure world separation via SMC calls and TZC-400 DDR address space controller; peripherals (GPIO, UART, I2C) are assigned secure attributes via ETZPC; and BSEC fuses lock secure boot configuration. This creates hardware-enforced boundaries for secure firmware, cryptographic keys, and real-time tasks.
What is the maximum resolution supported by the LTDC controller?
The LTDC controller supports up to WXGA (1366 × 768) at 60 fps or Full HD (1920 × 1080) at 30 fps with pixel clock up to 90 MHz. It features two independent layers with alpha blending, programmable color LUTs, and dithering - enabling smooth transitions and high-fidelity color reproduction without external graphics memory.
STM32MP153AAC3T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 361-TFBGA
- Series:
- STM32MP1
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A7
- Number of Cores/Bus Width:
- 2 Core, 32-Bit
- Speed:
- 209MHz, 650MHz
- Co-Processors/DSP:
- ARM® Cortex®-M4
- RAM Controllers:
- DDR3, DDR3L, LPDDR2, LPDDR3
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- HDMI-CEC, LCD
- Ethernet:
- 10/100Mbps (1)
- SATA:
- -
- USB:
- USB 2.0 (2), USB 2.0 OTG+ PHY (3)
- Voltage - I/O:
- 2.5V, 3.3V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- ARM TZ
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 361-TFBGA (12x12)
- Additional Interfaces:
- CAN, Ethernet, I2C, MMC/SD/SDIO, SPDIF, SPI, UART, USB
STM32MP153AAC3T FAQ
1.How can I place an order for STM32MP153AAC3T through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32MP153AAC3T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32MP153AAC3T reliable?
The price and inventory of STM32MP153AAC3T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32MP153AAC3T is usually 5 days.
3.What payment methods are accepted for STM32MP153AAC3T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32MP153AAC3T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32MP153AAC3T?
STM32MP153AAC3T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32MP153AAC3T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32MP153AAC3T?
For technical support, including STM32MP153AAC3T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32MP153AAC3T requirements.
6.How does Aetrix verify that STM32MP153AAC3T is sourced from the original manufacturer or authorized distributors?
All STM32MP153AAC3T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32MP153AAC3T meets industry standards.
7.What is the process for return or replacement of STM32MP153AAC3T?
All STM32MP153AAC3T units undergo pre-shipment inspection (PSI). If there is an issue with STM32MP153AAC3T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32MP153AAC3T part is unused and in its original packaging.
Return procedure for STM32MP153AAC3T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32MP153AAC3T Tags

-
AT91SAM9260B-CU-999
Microchip Technology

-
AT91SAM9G25-CU
Microchip Technology

-
ATSAMA5D27C-CU
Microchip Technology

-
AT91SAM9X35-CU
Microchip Technology

-
AT91SAM9X25-CU
Microchip Technology

-
MCIMX6Y2CVM08AB
NXP Semiconductors
-
AM3352BZCZ100
Texas Instruments

-
AT91SAM9260B-CU
Microchip Technology

-
AT91SAM9260B-QU
Microchip Technology

-
ATSAMA5D31A-CU
Microchip Technology

-
AT91SAM9G20B-CU-999
Microchip Technology

-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

