STMicroelectronics STM32MP153CAB3
- Part No.:
- STM32MP153CAB3
- Manufacturer:
- STMicroelectronics
- Category:
- Microprocessors
- Package:
- 354-LFBGA
- Datasheet:
-
STM32MP153CAB3.pdf
- Description:
- IC MPU STM32MP1 650MHZ 354LFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:4,899
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32MP153CAB3 from STMicroelectronics is a dual-core Arm® Cortex®-A7 (800 MHz) + Cortex®-M4 microprocessor unit (MPU) with TrustZone®, NEON™, and hardware crypto acceleration (AES/SHA/HMAC/RNG). It integrates TFT LCD controller (up to 1920×1080@30 fps), 2×16-bit ADCs (up to 4.5 Msps), 2×12-bit DACs, dual CAN FD (one TTCAN), and Gigabit Ethernet MAC - deployed in industrial HMIs, edge gateways, and smart building controllers.
For engineers reviewing the STM32MP153CAB3 datasheet, STM32MP153CAB3 pinout, STM32MP153CAB3 application, or STM32MP153CAB3 equivalent, key selection criteria include dual-core asymmetric processing capability, DDR3/LPDDR3 memory support up to 1 Gbyte, 176 I/Os with secure/tamper functions, and hardware-enforced security via TrustZone® and secure boot.
Technical Context
The STM32MP153CAB3 implements a heterogeneous dual-core architecture: two Cortex®-A7 cores run Linux-based applications with 256-Kbyte unified L2 cache and Arm® NEON™ for signal processing, while the Cortex®-M4 (209 MHz) handles real-time control tasks with FPU and MPU isolation. TrustZone® enforces strict memory and peripheral access partitioning between secure and non-secure worlds.
Its interconnect matrix comprises a 64-bit AXI bus (266 MHz) and 32-bit AHB bus (209 MHz), supporting concurrent high-bandwidth peripherals including GMAC, USB 2.0 HS Host/OTG, SDMMC (eMMC™/SDIO), and HDMI-CEC. The DDR controller supports LPDDR2/LPDDR3-1066 and DDR3/DDR3L-1066 at 16/32-bit widths with hardware ECC.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual Arm® Cortex®-A7 @ 800 MHz + single Cortex®-M4 @ 209 MHz - enables Linux + RTOS coexistence with hardware-isolated execution environments. |
| Memory Support | Up to 1 Gbyte external DDR (LPDDR2/LPDDR3-1066 or DDR3/DDR3L-1066); 708 Kbytes on-chip SRAM (256 KB AXI SYSRAM + 384 KB AHB SRAM + 64 KB Backup SRAM) - eliminates need for external RAM in many HMI designs. |
| Graphics & Display | LCD-TFT controller supporting WXGA (1366×768@60 fps) or Full HD (1920×1080@30 fps); 24-bit RGB888 interface with dual programmable color LUTs - drives high-resolution industrial panels without external GPU. |
| Analog Peripherals | 2×16-bit ADCs (12-bit @ 4.5 Msps, 16-bit @ 3.6 Msps), 2×12-bit DACs (1 MHz), DFSDM with 8 channels, internal temp sensor - enables precision sensor fusion and analog I/O in edge nodes. |
| Communication Interfaces | 6×I²C FM+, 8×UART/USART, 6×SPI (3 with I²S audio accuracy), 4×SAI, 2×CAN FD (1 TTCAN), 2×USB 2.0 HS Host + 1×USB 2.0 FS OTG, Gigabit Ethernet GMAC - supports multi-protocol industrial connectivity stack. |
| Security Features | Arm® TrustZone®, secure boot, active tamper detection, 3072-bit fuses (96-bit UID), AES-128/192/256, SHA-256, HMAC, dual TRNG - meets IEC 62443-3-3 SL2 requirements for secure firmware updates and data confidentiality. |
| Power Management | 1.71–3.6 V I/O supply (5 V-tolerant), Standby mode current down to 2 µA (no RTC/LSE/BKPSRAM/RETRAM), DDR retention in Standby - enables battery-backed operation in low-power edge devices. |
Pinout & Package
STM32MP153CAB3 is packaged in TFBGA361 (12 × 12 mm, 0.5 mm pitch), RoHS-compliant and ECOPACK2 certified. Pin definitions follow ST's B031 package marking (DS12503 Rev 9, Section 7.4).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDCORE | Core power supply | 1.1 V nominal supply for CPU cores and L2 cache; requires tight regulation (±3%) and low-noise filtering per DS12503 Section 6.3.5. |
| VDDIO | I/O power supply | 1.71–3.6 V supply enabling 5 V-tolerant operation; supports mixed-voltage system interfacing without level shifters. |
| NRST | Asynchronous reset input | Active-low reset pin asserting full chip reset; synchronized internally to avoid metastability during power sequencing. |
| BOOT0 | Boot mode selection | Configures primary boot source (eMMC, SD card, NAND, QSPI, USB) at power-up; sampled at POR and latched. |
| OSC_IN / OSC_OUT | External crystal oscillator inputs | Supports 8–48 MHz HSE and 32.768 kHz LSE crystals; critical for precise clock tree derivation and RTC accuracy. |
| ETH_MDIO / ETH_MDC | Ethernet management interface | IEEE 802.3-compliant MDIO/MDC interface for PHY configuration and status monitoring in GMAC subsystem. |
Key Features
| Feature | Design Value |
|---|---|
| Asymmetric Dual-Core Processing | Linux-capable Cortex-A7 cores handle UI/networking; Cortex-M4 executes deterministic real-time control loops - no RTOS latency penalty on application core. |
| Hardware Security Partitioning | TrustZone® address space controller (TZC) and embedded TrustZone protection controller (ETZPC) enforce memory/peripheral access boundaries - prevents unauthorized access to secure firmware or keys. |
| Integrated Graphics Acceleration | LCD-TFT controller with dual layer blending, alpha blending, and programmable gamma correction - reduces CPU load for GUI rendering in resource-constrained HMIs. |
| Flexible Memory Interface | Dual-mode Quad-SPI + Flexible Memory Controller (FMC) supporting SLC NAND (8-bit ECC) and parallel NOR/PSRAM - enables boot-from-NAND and local code/data storage without external flash controller. |
| Industrial Communication Stack | 2×CAN FD (one time-triggered), 3×SDMMC (eMMC™/SDIO), SPDIF Rx (4 inputs), HDMI-CEC - satisfies protocol diversity in factory automation and building management systems. |
Applications
| Industrial HMI | Edge Gateway |
|---|---|
Use Scenario: Touch-enabled operator panel in PLC-controlled machinery with local data logging and remote diagnostics. IC Role / Device Role / Timing Role: MPU hosts Qt-based GUI on Linux, runs Modbus TCP gateway, and manages real-time motion control via Cortex-M4. Use Value: Single-chip integration replaces discrete SoC+FPGA+PMIC solution, reducing BOM cost by ~32% and board area by 45% versus legacy ARM9+XC3S200 design. |
Use Scenario: Field-deployed protocol translator aggregating CAN FD, RS-485, and BLE sensor data into MQTT over cellular/Wi-Fi. IC Role / Device Role / Timing Role: Cortex-A7 runs OpenWrt with Mosquitto broker and protocol stacks; Cortex-M4 handles time-critical CAN FD frame scheduling and CRC validation. Use Value: Hardware-accelerated crypto (AES/SHA) enables TLS 1.2 offload for secure cloud uplinks without CPU overhead - maintains >15 Mbps throughput under encryption load. |
| Smart Building Controller | Medical Imaging Front-End |
Use Scenario: HVAC and lighting controller with occupancy sensing, energy metering, and BACnet/IP compliance. IC Role / Device Role / Timing Role: MPU executes BACnet stack and web server; integrated ADCs digitize temperature/humidity sensors; DACs drive analog valve actuators. Use Value: On-chip 16-bit ADCs (4.5 Msps) eliminate external precision ADC IC, reducing analog front-end component count by 7 parts and improving thermal drift stability. |
Use Scenario: Portable ultrasound device requiring real-time beamforming, RF signal conditioning, and DICOM export. IC Role / Device Role / Timing Role: Cortex-M4 performs FPGA-like timing-critical beam steering calculations; SAI interfaces with audio codec; DCMI captures raw sensor frames. Use Value: Dual Quad-SPI interface boots from encrypted QSPI flash while DFSDM processes sigma-delta microphone array data - achieves <10 µs jitter in time-of-flight measurements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core MPU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXP i.MX 8M Mini (LQM) | Quad Cortex-A53 + Cortex-M4; lacks TrustZone®-enabled DDR controller and integrated TFT controller; higher typical power (3.2 W vs. 1.8 W @ full load). | Better for Android-based multimedia; less suitable for safety-critical display control due to absence of hardware display compositor. | Select when Android NDK development or quad-core compute density outweighs display/crypto/security integration needs. |
| Renesas RZ/G2L | Dual Cortex-A55 + Cortex-M33; includes DRAM-less LPDDR4x support but no built-in CAN FD or HDMI-CEC; lower analog integration (no DACs, single 12-bit ADC). | Optimized for vision AI inference (NPU); weaker for mixed-signal industrial control requiring simultaneous analog I/O and fieldbus comms. | Prefer for camera-centric edge AI; avoid where CAN FD, dual DACs, or TFT controller are mandatory. |
Compared with i.MX 8M Mini and RZ/G2L, the STM32MP153CAB3 delivers superior integration for display-rich industrial controllers - combining TFT controller, dual CAN FD, hardware crypto, and analog peripherals in one die, reducing external component count and simplifying functional safety certification.
Availability
STM32MP153CAB3 is available at Aetrix Electronics and suitable for industrial HMIs, edge gateways, and smart building controllers requiring stable component supply across 10+ year product lifecycles.
Supply support for STM32MP153CAB3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive-grade components since 1987.
The STM32MP series targets heterogeneous computing in industrial and IoT edge applications, combining Linux-capable application processors with real-time microcontroller cores and hardware security - specifically engineered for secure, display-intensive, protocol-diverse embedded systems.
FAQ
What boot sources does the STM32MP153CAB3 support?
The STM32MP153CAB3 supports boot from eMMC™, SD card, NAND Flash (SLC with 8-bit ECC), Quad-SPI NOR/NAND, USB mass storage, and UART. Boot mode is selected via BOOT0 pin and optional BOOT1 strap; configuration is validated by ROM code before executing FSBL from selected medium.
Does the STM32MP153CAB3 require an external PMIC?
No - it integrates multiple on-chip LDOs (1.1 V for core, 1.8 V for USB, 1.8 V for RETRAM, 0.9 V backup regulator) and supports direct connection to single 3.3 V or 5 V input. External PMIC is optional for advanced power sequencing or multi-rail optimization in high-reliability systems.
How is TrustZone® implemented on this device?
TrustZone® is implemented via hardware-enforced memory isolation using the TrustZone Address Space Controller (TZC) for DDR and Embedded TrustZone Protection Controller (ETZPC) for peripherals. Secure monitor firmware (TF-A) manages world switching; secure boot validates chain-of-trust from ROM loader through OP-TEE and Linux kernel.
What is the maximum resolution supported by the LTDC controller?
The LCD-TFT Display Controller (LTDC) supports up to Full HD (1920 × 1080) at 30 fps or WXGA (1366 × 768) at 60 fps, with pixel clock up to 90 MHz. It features dual layers, alpha blending, color LUTs, and dithering - enabling rich GUIs without external graphics accelerator.
STM32MP153CAB3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 354-LFBGA
- Series:
- STM32MP1
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A7
- Number of Cores/Bus Width:
- 2 Core, 32-Bit
- Speed:
- 209MHz, 650MHz
- Co-Processors/DSP:
- ARM® Cortex®-M4
- RAM Controllers:
- DDR3, DDR3L, LPDDR2, LPDDR3
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- HDMI-CEC, LCD
- Ethernet:
- 10/100Mbps (1)
- SATA:
- -
- USB:
- USB 2.0 (2), USB 2.0 OTG+ PHY (3)
- Voltage - I/O:
- 2.5V, 3.3V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- ARM TZ
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 354-LFBGA (16x16)
- Additional Interfaces:
- CAN, Ethernet, I2C, MMC/SD/SDIO, SPDIF, SPI, UART, USB
STM32MP153CAB3 FAQ
1.How can I place an order for STM32MP153CAB3 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32MP153CAB3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32MP153CAB3 reliable?
The price and inventory of STM32MP153CAB3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32MP153CAB3 is usually 5 days.
3.What payment methods are accepted for STM32MP153CAB3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32MP153CAB3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32MP153CAB3?
STM32MP153CAB3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32MP153CAB3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32MP153CAB3?
For technical support, including STM32MP153CAB3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32MP153CAB3 requirements.
6.How does Aetrix verify that STM32MP153CAB3 is sourced from the original manufacturer or authorized distributors?
All STM32MP153CAB3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32MP153CAB3 meets industry standards.
7.What is the process for return or replacement of STM32MP153CAB3?
All STM32MP153CAB3 units undergo pre-shipment inspection (PSI). If there is an issue with STM32MP153CAB3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32MP153CAB3 part is unused and in its original packaging.
Return procedure for STM32MP153CAB3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32MP153CAB3 Tags

-
AT91SAM9260B-CU-999
Microchip Technology

-
AT91SAM9G25-CU
Microchip Technology

-
ATSAMA5D27C-CU
Microchip Technology

-
AT91SAM9X35-CU
Microchip Technology

-
AT91SAM9X25-CU
Microchip Technology

-
MCIMX6Y2CVM08AB
NXP Semiconductors
-
AM3352BZCZ100
Texas Instruments

-
AT91SAM9260B-CU
Microchip Technology

-
AT91SAM9260B-QU
Microchip Technology

-
ATSAMA5D31A-CU
Microchip Technology

-
AT91SAM9G20B-CU-999
Microchip Technology

-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

