STMicroelectronics STM32MP153DAC1

Overview

STM32MP153DAC1 from STMicroelectronics is a dual-core Arm® Cortex®-A7 (800 MHz) + Cortex®-M4 microprocessor unit (MPU) with TrustZone® security, TFT LCD controller, 37 communication interfaces, 29 timers, and advanced analog peripherals. It integrates 708 KB of on-chip SRAM, supports LPDDR2/LPDDR3-1066 and DDR3/DDR3L-1066 external memory up to 1 GB, and delivers 2 µA Standby current consumption. It targets industrial HMI, edge gateway, and secure embedded Linux applications requiring real-time co-processing.

For engineers reviewing the STM32MP153DAC1 datasheet, STM32MP153DAC1 pinout, STM32MP153DAC1 application, or STM32MP153DAC1 equivalent, this page provides verified technical context, validated pin functions, confirmed low-power mode behavior, and documented CAN FD/TTCAN and dual USB 2.0 HS/FS OTG support - all critical for Linux BSP bring-up, power budgeting, and secure peripheral partitioning.

Technical Context

The device implements a heterogeneous dual-core architecture: two Cortex®-A7 cores run Linux in non-secure world with 256 KB unified L2 cache and NEON™ acceleration, while the Cortex®-M4 (209 MHz) handles real-time tasks in secure isolation via TrustZone®. Memory subsystem includes AXI SYSRAM (256 KB), AHB SRAM (384 KB), and 4 KB backup SRAM - all mapped to distinct bus matrices (64-bit AXI @266 MHz, 32-bit AHB @209 MHz).

Communication infrastructure features six I²C FM+ ports, four UARTs + four USARTs (12.5 Mbit/s), six SPIs (50 Mbit/s, three with I²S audio-class accuracy), four SAI interfaces, dual CAN FD controllers (one TTCAN-capable), and Gigabit Ethernet GMAC with IEEE 1588v2 hardware timestamping - enabling deterministic industrial networking and multi-channel audio processing.

Key Specifications

Pinout & Package

STM32MP153DAC1 is packaged in a TFBGA361 (12 × 12 mm, 0.5 mm pitch) ball grid array, compliant with ECOPACK2 environmental standards. Pin functions are validated per ST's DS12502 Rev 9 datasheet Section 4 (Pinouts, pin description and alternate functions) and Table 7 (pin and ball definitions).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar MPU applications.

Compared with STM32MP157CAC1, the STM32MP153DAC1 trades PCIe and extra Ethernet for lower thermal envelope (2 µA Standby vs. 3.5 µA) and tighter TTCAN timing control - making it optimal for cost-sensitive, battery-powered industrial HMIs where deterministic real-time response is prioritized over expansion bandwidth.

Availability

STM32MP153DAC1 is available at Aetrix Electronics and suitable for industrial HMI, edge gateway, and secure medical data logger applications requiring stable component supply across 10+ year product lifecycles.

Supply support for STM32MP153DAC1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog devices for industrial, automotive, and consumer markets.

The STM32MP series is ST's heterogeneous MPU product line targeting Linux-capable embedded systems with real-time co-processing, security, and rich peripheral integration - specifically engineered for industrial automation, smart infrastructure, and secure IoT endpoints.

FAQ

What boot sources does STM32MP153DAC1 support?

STM32MP153DAC1 supports boot from eMMC, SD card, Quad-SPI flash, USB device, and UART via its internal ROM bootloader. Boot mode is selected using BOOT0 and BOOT1 pins per Table 2 in DS12502 Rev 9. The device also supports signed image authentication using embedded public keys stored in OTP fuses.

Does STM32MP153DAC1 include hardware support for real-time Linux scheduling?

Yes - it includes two Cortex-A7 system timers (secure and non-secure), a virtual timer, and hypervisor timer, plus hardware semaphore (HSEM) and inter-processor communication controller (IPCC) for efficient A7/M4 synchronization. These enable PREEMPT_RT patchset integration and sub-100 µs interrupt latency in verified Yocto builds.

How is TrustZone® implemented across the dual-core architecture?

TrustZone® is implemented at silicon level: the Cortex-A7 cores use TrustZone® address space controller (TZC) for DDR memory protection, while the ETZPC peripheral gates access to peripherals based on secure/non-secure state. The Cortex-M4 operates exclusively in secure world, with dedicated SRAM and interrupt routing - validated in ST's AN5131 application note.

What is the maximum pixel clock frequency supported by the LTDC controller?

The LCD-TFT display controller (LTDC) supports a maximum pixel clock of 90 MHz, enabling WXGA (1366×768) resolution at 60 fps or Full HD (1920×1080) at 30 fps. This is specified in Section 3.29 of DS12502 Rev 9 and confirmed by electrical characteristics in Table 6.3.34 (LTDC timing parameters).