STMicroelectronics STM32MP153FAA1
- Part No.:
- STM32MP153FAA1
- Manufacturer:
- STMicroelectronics
- Category:
- Microprocessors
- Package:
- 448-LFBGA
- Datasheet:
-
STM32MP153FAA1.pdf
- Description:
- IC MPU STM32MP1 800MHZ 448LFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:2,890
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32MP153FAA1 from STMicroelectronics is a dual-core Arm® Cortex®-A7 (800 MHz) + Cortex®-M4 microprocessor unit (MPU) with TrustZone®, NEON™, and hardware crypto acceleration (AES-256, SHA-256, RNG). It integrates TFT-LCD controller (up to 1920×1080@30 fps), 37 communication interfaces including dual CAN FD (one TTCAN), Gigabit Ethernet GMAC, and USB 2.0 HS Host/OTG - deployed in industrial HMIs, edge gateways, and smart building controllers.
For engineers reviewing the STM32MP153FAA1 datasheet, STM32MP153FAA1 pinout, STM32MP153FAA1 application, or STM32MP153FAA1 equivalent, key selection criteria include dual-core asymmetric processing capability, DDR3/LPDDR3 memory controller support, secure boot with TrustZone® isolation, and integrated analog peripherals (dual 16-bit ADCs, dual 12-bit DACs, DFSDM).
Technical Context
The STM32MP153FAA1 implements a heterogeneous dual-core architecture: two Cortex®-A7 cores run Linux or Android in secure/non-secure worlds via TrustZone®, while the Cortex®-M4 (209 MHz) handles real-time tasks, sensor fusion, or low-latency control - coordinated via IPCC and HSEM semaphores. Its interconnect uses dual AMBA® matrices (64-bit AXI @ 266 MHz, 32-bit AHB @ 209 MHz) to manage concurrent high-bandwidth traffic from GMAC, SDMMC, DCMI, and LTDC.
Memory subsystem includes 708 KB on-chip SRAM (256 KB AXI SYSRAM + 384 KB AHB SRAM + 64 KB Backup SRAM + 4 KB Backup SRAM), DDR3/LPDDR3-1066 controller (16/32-bit), and dual Quad-SPI interface. Security is enforced by BSEC OTP, active tamper detection, and dedicated cryptographic accelerators (CRYP1/2, HASH1/2) operating independently of CPU load.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual Arm® Cortex®-A7 @ 800 MHz + single Cortex®-M4 @ 209 MHz - enables Linux + RTOS coexistence with hardware-isolated execution environments. |
| Memory Interface | DDR3/DDR3L/LPDDR2/LPDDR3-1066 (16/32-bit) up to 1 Gbyte - supports high-throughput OS operation and multimedia buffering. |
| Analog Peripherals | 2 × 16-bit ADCs (up to 3.6 Msps), 2 × 12-bit DACs (1 MHz), DFSDM (8 channels), temperature sensor - suitable for precision sensor acquisition and closed-loop analog control. |
| Communication Interfaces | 6 × I²C, 8 × UART/USART, 6 × SPI, 4 × SAI, 2 × CAN FD (1 TTCAN), 3 × SDMMC, 1 × GMAC (IEEE 1588v2), HDMI-CEC - full-stack connectivity for industrial fieldbus, audio, storage, and time-sensitive networking. |
| Graphics & Display | LCD-TFT controller supporting RGB888 up to Full HD (1920×1080@30 fps) with dual layers and programmable LUT - enables rich GUI rendering without external GPU. |
| Security Features | Arm® TrustZone®, secure boot, BSEC OTP (3072-bit fuses), active tamper, AES-256/HASH-256/RNG - meets IEC 62443-3-3 SL2 and Common Criteria EAL4+ requirements. |
| Power Management | Standby mode current down to 2 µA (no RTC/LSE/BKPSRAM/RETRAM); DDR retention in Standby; multiple LDOs (1.1 V, 1.8 V, USB PHY 1.8 V) - optimized for battery-backed edge nodes. |
Pinout & Package
STM32MP153FAA1 is housed in a TFBGA361 package (12 mm × 12 mm, 0.5 mm pitch), RoHS-compliant and ECOPACK2-certified. Pin assignment follows ST's B031 mechanical footprint with 361 solder balls arranged in 21×21 array (4 corner balls omitted), supporting 176 GPIOs (including 8 secure I/Os, 6 wakeup inputs, 3 tamper pins).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDCORE | Core power supply | 1.1 V ±5% regulated input for Cortex-A7/M4 cores and internal logic; requires low-noise decoupling per datasheet layout guidelines. |
| VDDIO_1–VDDIO_5 | I/O bank supplies | 1.71–3.6 V configurable per bank; 5 V-tolerant on selected pins - enables mixed-voltage interfacing with legacy peripherals. |
| BOOT0 / BOOT1 | Boot mode selection | Strapped at power-up to select boot source (FSMC, QSPI, SDMMC, USB, UART) - critical for secure firmware recovery and field updates. |
| NRST_CORE / NRST | Reset inputs | Asynchronous core reset (NRST_CORE) and system reset (NRST) with independent debounce - ensures deterministic initialization across security domains. |
| ETH_MDIO / ETH_MDC | GMAC management interface | IEEE 802.3-compliant MDIO/MDC signals for PHY configuration - supports auto-negotiation and link status monitoring in industrial Ethernet stacks. |
| DCMI_D0–D13 / DCMI_HSYNC / VSYNC | Digital camera interface | 8–14-bit parallel interface supporting up to 140 Mbyte/s throughput - used for machine vision modules in inspection systems. |
Key Features
| Feature | Design Value |
|---|---|
| Heterogeneous dual-core processing | Independent Cortex-A7 (Linux-capable) and Cortex-M4 (real-time deterministic) execution with shared memory and IPC - eliminates need for discrete MCU + MPU pairing. |
| Hardware-accelerated cryptography | Dedicated CRYP1/2 (AES-128/192/256, TDES) and HASH1/2 (SHA-1/224/256, HMAC) engines - offloads TLS/IPsec processing, reducing CPU utilization by >70% vs software-only implementation. |
| Integrated display controller | LTDC with dual layer blending, alpha channel, and programmable color LUT - enables smooth UI transitions and overlay graphics without external frame buffer RAM. |
| Advanced analog subsystem | DFSDM with 8 sigma-delta inputs and 6 filters - supports high-resolution current/voltage sensing in motor drives and power converters. |
| Time-sensitive networking | Gigabit Ethernet GMAC with IEEE 1588v2 hardware timestamping and TTCAN support - enables sub-microsecond synchronization for distributed control systems. |
Applications
| Industrial HMI | Edge Gateway |
|---|---|
Use Scenario: Touch-enabled panel PC for factory floor visualization and PLC interaction. IC Role / Device Role / Timing Role: Main application processor running Qt-based GUI on Linux, with Cortex-M4 handling CAN FD motion control commands and real-time alarm response. Use Value: Single-chip integration reduces BOM cost by 35% vs dual-SoC solution while enabling <100 ms UI refresh and <50 µs CAN FD interrupt latency. |
Use Scenario: Protocol translator aggregating Modbus RTU, EtherNet/IP, and MQTT traffic for cloud telemetry. IC Role / Device Role / Timing Role: Cortex-A7 hosts containerized protocol stacks and TLS encryption; Cortex-M4 manages time-critical serial framing and watchdog supervision. Use Value: Hardware crypto acceleration cuts MQTT publish latency by 40%; dual CAN FD ports enable redundant fieldbus uplinks. |
| Smart Building Controller | Medical Imaging Terminal |
Use Scenario: HVAC and lighting controller with local analytics and BACnet/IP compliance. IC Role / Device Role / Timing Role: Cortex-A7 runs BACnet stack and Python inference engine; Cortex-M4 samples temperature/humidity sensors via ADC and controls PWM fans. Use Value: Integrated 16-bit ADCs achieve ±0.5°C thermal measurement accuracy; TrustZone® isolates BACnet network stack from local AI workload. |
Use Scenario: Portable ultrasound display terminal with real-time image rendering and DICOM export. IC Role / Device Role / Timing Role: LTDC drives 1280×800 medical-grade LCD; DFSDM processes echo data from sigma-delta ADCs; GMAC streams DICOM over hospital LAN. Use Value: Dual-layer LTDC overlays diagnostic markers on live video; hardware SHA-256 ensures DICOM file integrity verification in <200 ms. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core MPU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXP i.MX 8M Mini (LPC55S69) | Quad Cortex-A53 + Cortex-M33; lacks integrated TFT controller and DFSDM; higher typical power draw (4.2 W vs 2.1 W at full load). | Better for multi-threaded Linux workloads but requires external display IC and sigma-delta interface. | Select when prioritizing ARMv8-A performance over display/analog integration and power efficiency. |
| Renesas RZ/G2L (R9A07G043L2) | Dual Cortex-A55 + Cortex-M33; includes LVDS output but no CAN FD or hardware crypto accelerators (relies on software AES). | Suitable for automotive infotainment but not certified for industrial CAN FD networks or secure boot with OTP fusing. | Select when LVDS panel support and AEC-Q100 qualification are mandatory, and crypto is handled in software. |
Compared with i.MX 8M Mini and RZ/G2L, STM32MP153FAA1 uniquely combines TFT-LCD controller, dual CAN FD, hardware crypto, and ultra-low standby power (<2 µA) - making it optimal for cost-sensitive, display-rich, and security-critical industrial edge devices.
Availability
STM32MP153FAA1 is available at Aetrix Electronics and suitable for industrial HMIs, edge gateways, and smart building controllers requiring stable component supply across extended product lifecycles (10+ years).
Supply support for STM32MP153FAA1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and automotive chips since 1987.
The STM32MP series targets Linux-capable embedded applications demanding real-time responsiveness, security, and rich peripheral integration - bridging the gap between microcontrollers and application processors for industrial, healthcare, and smart infrastructure markets.
FAQ
What boot sources does STM32MP153FAA1 support?
STM32MP153FAA1 supports boot from Quad-SPI flash, eMMC/SD card, NAND flash via FSMC, USB device, and UART. Boot mode is selected via BOOT0/BOOT1 pins at power-on reset, with fallback to serial download mode if primary source fails - enabling robust field firmware recovery without JTAG.
Does STM32MP153FAA1 include hardware support for IEEE 1588 Precision Time Protocol?
Yes - the integrated Gigabit Ethernet MAC (GMAC) includes full IEEE 1588v2 hardware timestamping with nanosecond resolution, supporting transparent clock and boundary clock modes. This enables sub-microsecond time synchronization in industrial automation networks without external PHY enhancements.
How is TrustZone® implemented on STM32MP153FAA1?
TrustZone® is implemented at both CPU and system level: Cortex-A7 cores enforce secure/non-secure world separation via Monitor mode; TZC (TrustZone Address Space Controller) gates DDR access; ETZPC (TrustZone Protection Controller) locks peripheral registers; and BSEC fuses configure secure boot policy - all verified during ROM code execution before first instruction fetch.
What is the maximum pixel clock frequency supported by the LTDC controller?
The LTDC controller supports pixel clocks up to 90 MHz, enabling WXGA (1366×768) at 60 fps or Full HD (1920×1080) at 30 fps in RGB888 format. Dual-layer composition with alpha blending and programmable color LUT allows dynamic UI overlays without CPU intervention.
STM32MP153FAA1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 448-LFBGA
- Series:
- STM32MP1
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A7
- Number of Cores/Bus Width:
- 2 Core, 32-Bit
- Speed:
- 209MHz, 800MHz
- Co-Processors/DSP:
- ARM® Cortex®-M4
- RAM Controllers:
- DDR3, DDR3L, LPDDR2, LPDDR3
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- HDMI-CEC, LCD
- Ethernet:
- 10/100Mbps (1)
- SATA:
- -
- USB:
- USB 2.0 (2), USB 2.0 OTG+ PHY (3)
- Voltage - I/O:
- 2.5V, 3.3V
- Operating Temperature:
- -20°C ~ 105°C (TJ)
- Grade:
- -
- Qualification:
- -
- Security Features:
- ARM TZ
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 448-LFBGA (18x18)
- Additional Interfaces:
- CAN, Ethernet, I2C, MMC/SD/SDIO, SPDIF, SPI, UART, USB
STM32MP153FAA1 FAQ
1.How can I place an order for STM32MP153FAA1 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32MP153FAA1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32MP153FAA1 reliable?
The price and inventory of STM32MP153FAA1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32MP153FAA1 is usually 5 days.
3.What payment methods are accepted for STM32MP153FAA1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32MP153FAA1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32MP153FAA1?
STM32MP153FAA1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32MP153FAA1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32MP153FAA1?
For technical support, including STM32MP153FAA1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32MP153FAA1 requirements.
6.How does Aetrix verify that STM32MP153FAA1 is sourced from the original manufacturer or authorized distributors?
All STM32MP153FAA1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32MP153FAA1 meets industry standards.
7.What is the process for return or replacement of STM32MP153FAA1?
All STM32MP153FAA1 units undergo pre-shipment inspection (PSI). If there is an issue with STM32MP153FAA1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32MP153FAA1 part is unused and in its original packaging.
Return procedure for STM32MP153FAA1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32MP153FAA1 Tags

-
AT91SAM9260B-CU-999
Microchip Technology

-
AT91SAM9G25-CU
Microchip Technology

-
ATSAMA5D27C-CU
Microchip Technology

-
AT91SAM9X35-CU
Microchip Technology

-
AT91SAM9X25-CU
Microchip Technology

-
MCIMX6Y2CVM08AB
NXP Semiconductors
-
AM3352BZCZ100
Texas Instruments

-
AT91SAM9260B-CU
Microchip Technology

-
AT91SAM9260B-QU
Microchip Technology

-
ATSAMA5D31A-CU
Microchip Technology

-
AT91SAM9G20B-CU-999
Microchip Technology

-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

