STMicroelectronics STM32MP157CAD3
- Part No.:
- STM32MP157CAD3
- Manufacturer:
- STMicroelectronics
- Category:
- Microprocessors
- Package:
- 257-TFBGA
- Datasheet:
-
STM32MP157CAD3.pdf
- Description:
- IC MPU STM32MP1 650MHZ 257TFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:954
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Product details
Overview
STM32MP157CAD3 from STMicroelectronics is a dual-core Arm® Cortex®-A7 (800 MHz) + Cortex®-M4 microprocessor unit with 3D GPU, TFT/DSI display support, 37 communication interfaces, 29 timers, advanced analog peripherals, and hardware crypto acceleration. It integrates 708 KB on-chip SRAM, TrustZone® security, and supports LPDDR2/LPDDR3/DDR3 up to 1 Gbyte for industrial HMI, edge gateway, and smart appliance control applications.
For engineers reviewing the STM32MP157CAD3 datasheet, STM32MP157CAD3 pinout, STM32MP157CAD3 application, or STM32MP157CAD3 equivalent, key selection criteria include dual-core Linux-capable architecture, 2× CAN FD with TTCAN support, MIPI DSI 2-lane 1 Gbps interface, Vivante® 3D GPU performance (26 Mtriangle/s), and 176 I/Os with secure/tamper capability.
Technical Context
The device implements a heterogeneous dual-core architecture: two Cortex-A7 cores run Linux or Android in non-secure world with 256 KB unified L2 cache and NEON™/TrustZone®, while the Cortex-M4 (209 MHz) handles real-time tasks, sensor fusion, or secure firmware in isolated memory space. Inter-core communication uses IPCC and hardware semaphores.
Clock management includes six fractional PLLs supporting precise frequency synthesis for DDR, USB, DSI, audio, and Ethernet domains; power management enables DDR retention in Standby mode with total system current as low as 2 µA - critical for battery-backed industrial gateways and always-on UI systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual Arm® Cortex®-A7 @ 800 MHz + single Cortex®-M4 @ 209 MHz - enables Linux + RTOS coexistence with hardware-isolated execution environments |
| GPU | Vivante® GC320 OpenGL® ES 2.0 - delivers 26 Mtriangle/s for smooth 1366×768@60 fps TFT rendering or 1920×1080@30 fps video overlay |
| Memory Interface | LPDDR2/LPDDR3/DDR3 controller up to 1066 MT/s, 16/32-bit bus - supports 1 GB external RAM with ECC-capable FMC for NAND/NOR expansion |
| Communication Peripherals | 2× CAN FD (1 with time-triggered TTCAN), 6× I²C FM+, 4× UART/USART, 6× SPI, 4× SAI, 3× SDMMC, 2× USB 2.0 HS Host + 1× FS OTG - full connectivity for industrial fieldbus, audio, storage, and peripheral bridging |
| Analog & Timing | 2× 16-bit ADCs (up to 3.6 Msps), 2× 12-bit DACs (1 MHz), 29 timers including RTC with sub-second accuracy and 5× low-power timers - suitable for precision sensor acquisition and motor control timing |
| Security | Arm® TrustZone®, secure boot, active tamper detection, 2× true RNG, AES-128/192/256, HASH (SHA256), HMAC - meets IEC 62443-3-3 SL2 requirements for embedded industrial security |
| Display Interface | MIPI® DSI 2-lane @ 1 Gbps/lane + LCD-TFT controller (24-bit RGB888, 90 MHz pixel clock) - drives high-resolution touch displays without external bridge ICs |
Pinout & Package
STM32MP157CAD3 is housed in a TFBGA361 package (12 × 12 mm, 0.5 mm pitch), RoHS-compliant and ECOPACK2 certified. Pin assignment follows B031 mechanical variant per ST's DS12505 Rev 9, with 361 solder balls arranged in 19×19 grid excluding corner blanks.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDCORE | Core power supply | 1.1 V ±5% regulated input for CPU/GPU logic; requires local 10 µF ceramic decoupling |
| VDDIO_1 | I/O bank 1 supply | 1.71–3.6 V tolerant rail powering GPIOs PB0–PB15, PC0–PC15, PD0–PD15 - supports mixed-voltage interfacing |
| NRST | System reset input | Active-low asynchronous reset; internal pull-up; compatible with external reset supervisor ICs like STM8TL52 |
| OSC_IN / OSC_OUT | External crystal oscillator terminals | Supports 8–48 MHz HSE crystal for precise system clock; required for USB/DSI/Ethernet timing compliance |
| BOOT0 | Boot mode selection | High at power-up selects internal Flash boot; tied low via 10 kΩ resistor enables serial boot from SD card or USB DFU |
| PA13 / PA14 | SWD debug interface | Serial Wire Debug (SWDIO/SWCLK) - enables JTAG/SWD debugging of both A7 and M4 cores simultaneously |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core asymmetric processing | Linux-capable Cortex-A7 cluster + deterministic real-time Cortex-M4 - eliminates need for companion MCU in gateway designs |
| Integrated 3D graphics acceleration | Vivante® GC320 GPU with OpenGL ES 2.0 - reduces BOM cost by removing external GPU or FPGA-based rendering engines |
| MIPI DSI 2-lane interface | 1 Gbps per lane with embedded D-PHY - enables direct connection to low-power, high-resolution display panels without level-shifting or timing-critical PCB routing |
| Hardware crypto engine | Dedicated AES/HASH/RNG blocks - accelerates TLS handshake, secure boot verification, and firmware update signing at line rate |
| Flexible memory subsystem | AXI SYSRAM (256 KB), AHB SRAM (384 KB), Backup SRAM (64 KB + 4 KB) - supports fast context switching, data logging during power loss, and secure key storage |
Applications
| Industrial HMI Panel | Edge Gateway Controller |
|---|---|
Use Scenario: 7-inch capacitive touchscreen panel in factory automation cabinet with real-time PLC communication and local web server. IC Role / Device Role / Timing Role: Main application processor running Yocto Linux, driving TFT display via LTDC, managing CAN FD fieldbus, and executing Modbus TCP over Gigabit Ethernet. Use Value: Dual-core isolation ensures UI responsiveness during heavy network load; DSI interface eliminates external display bridge IC, reducing layer count and EMI risk. | Use Scenario: Smart building gateway aggregating BACnet MS/TP, KNX, and LoRaWAN sensor data before forwarding to cloud via TLS-secured MQTT. IC Role / Device Role / Timing Role: Secure application host with TrustZone-enforced crypto operations, CAN FD and UART peripherals for legacy fieldbus translation, and hardware-accelerated SHA256 for certificate validation. Use Value: On-chip AES/HASH engines cut TLS handshake latency by >60% vs software-only implementation; 176 GPIOs allow direct attachment of multiple PHY transceivers without glue logic. |
| Smart Home Appliance | Medical Diagnostic Display |
Use Scenario: Wi-Fi-connected refrigerator with voice assistant, camera-based food recognition, and multi-zone temperature control dashboard. IC Role / Device Role / Timing Role: Application SoC running Android Things, processing camera input via DCMI, generating audio via SAI, and controlling PWM fans/motors using advanced timers. Use Value: Integrated 8–14-bit DCMI interface captures 140 MB/s raw image data; dual 12-bit DACs generate precise analog reference voltages for temperature sensor calibration. | Use Scenario: Portable ultrasound device requiring high-fidelity grayscale rendering, real-time beamforming offload, and HIPAA-compliant data encryption. IC Role / Device Role / Timing Role: Real-time imaging processor with Cortex-M4 handling time-critical beam steering, Cortex-A7 running UI and DICOM export, and GPU accelerating histogram equalization. Use Value: 29 timers include quadrature encoder inputs for motorized probe positioning; hardware RNG and AES-256 meet FDA cybersecurity guidance for Class II devices. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar MPU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXP i.MX 8M Mini (LPC54608) | Quad Cortex-A53 + Cortex-M4; lacks integrated 3D GPU and MIPI DSI; higher power envelope (3.5 W typical) | Better for headless edge AI inference; weaker for local GUI rendering and display integration | Select when prioritizing NPU acceleration over display bandwidth and lower standby power |
| Renesas RZ/G2L (R9A07G043L220BU) | Dual Cortex-A55 + Cortex-M33; includes 3D GPU but no TTCAN or DSI; supports only LPDDR4x | Stronger security certification path (PSA Level 2); limited industrial fieldbus support | Choose for automotive-grade functional safety projects requiring ASIL-B evidence packages |
Compared with i.MX 8M Mini and RZ/G2L, STM32MP157CAD3 uniquely balances Linux application capability, real-time M4 co-processing, MIPI DSI display integration, and industrial CAN FD/TTCAN - making it optimal for cost-sensitive, display-rich, fieldbus-connected edge devices where thermal envelope and standby power are constrained.
Availability
STM32MP157CAD3 is available at Aetrix Electronics and suitable for industrial HMI, edge gateway, and smart appliance applications requiring stable component supply, long-term lifecycle assurance, and qualified production traceability.
Supply support for STM32MP157CAD3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and analog products for industrial, automotive, and consumer markets.
The STM32MP series targets Linux-capable embedded applications demanding real-time responsiveness, graphical user interfaces, and hardware-enforced security - bridging the gap between microcontrollers and application processors.
FAQ
What boot sources does STM32MP157CAD3 support?
STM32MP157CAD3 supports eight boot modes selected via BOOT pins: eMMC/SD card, NAND Flash, Quad-SPI NOR Flash, USB mass storage, UART/USB DFU, and internal Flash. Boot sequence is managed by the ROM code and configurable via OTP bits in the BSEC block; secure boot verifies signed images using embedded public keys.
Does STM32MP157CAD3 require an external PMIC?
No - STM32MP157CAD3 integrates five on-die LDOs (1.1 V, 1.2 V, 1.8 V, RETRAM, BKPSRAM) and a backup regulator (~0.9 V), enabling direct connection to single 3.3 V or 5 V input. An external PMIC is optional for enhanced efficiency or dynamic voltage scaling in high-performance use cases.
How is TrustZone implemented across the dual-core architecture?
TrustZone is implemented at both silicon and firmware levels: the TZC-400 controller gates DDR access per core privilege level, while the ETZPC configures peripheral security attribution. The Cortex-A7 runs secure monitor (ARM Trusted Firmware) and OP-TEE OS in secure world; Cortex-M4 executes secure firmware independently, with inter-processor communication via IPCC mailboxes.
What display resolutions and interfaces are natively supported?
STM32MP157CAD3 natively supports WXGA (1366×768) @60 fps and Full HD (1920×1080) @30 fps via its LCD-TFT controller and MIPI DSI 2-lane interface. It also supports RGB666/888, LVDS (with external serializer), and HDMI-CEC - but HDMI video output requires external TFP410 or similar TMDS transmitter IC.
STM32MP157CAD3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 257-TFBGA
- Series:
- STM32MP1
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A7
- Number of Cores/Bus Width:
- 2 Core, 32-Bit
- Speed:
- 209MHz, 650MHz
- Co-Processors/DSP:
- ARM® Cortex®-M4
- RAM Controllers:
- DDR3, DDR3L, LPDDR2, LPDDR3
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- HDMI-CEC, LCD
- Ethernet:
- 10/100Mbps, GbE
- SATA:
- -
- USB:
- USB 2.0 (2), USB 2.0 OTG+ PHY (3)
- Voltage - I/O:
- 2.5V, 3.3V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- ARM TZ
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 257-TFBGA (10x10)
- Additional Interfaces:
- CAN, Ethernet, I2C, MMC/SD/SDIO, SPDIF, SPI, UART, USB
STM32MP157CAD3 FAQ
1.How can I place an order for STM32MP157CAD3 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32MP157CAD3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32MP157CAD3 reliable?
The price and inventory of STM32MP157CAD3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32MP157CAD3 is usually 5 days.
3.What payment methods are accepted for STM32MP157CAD3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32MP157CAD3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32MP157CAD3?
STM32MP157CAD3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32MP157CAD3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32MP157CAD3?
For technical support, including STM32MP157CAD3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32MP157CAD3 requirements.
6.How does Aetrix verify that STM32MP157CAD3 is sourced from the original manufacturer or authorized distributors?
All STM32MP157CAD3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32MP157CAD3 meets industry standards.
7.What is the process for return or replacement of STM32MP157CAD3?
All STM32MP157CAD3 units undergo pre-shipment inspection (PSI). If there is an issue with STM32MP157CAD3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32MP157CAD3 part is unused and in its original packaging.
Return procedure for STM32MP157CAD3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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