My Inquiry
My Account
STMicroelectronics STM32U535CBU6
- Part No.:
- STM32U535CBU6
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 48-UFQFN Exposed Pad
- Datasheet:
-
STM32U535CBU6.pdf
- Description:
- IC MCU 32BIT 128KB FLSH 48UFQFPN
- Quantity:
- Payment:
- Shipping:
Inventory:3,232
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32U535CBU6 from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 microcontroller with TrustZone® security, 240 DMIPS performance, 512 KB flash (ECC), 274 KB SRAM (64 KB with ECC), and integrated SMPS. It operates from 1.71–3.6 V across –40 °C to +125 °C and delivers 3.0 µA Stop 2 mode with 16-Kbyte SRAM for battery-powered industrial sensors and secure IoT edge nodes.
For engineers reviewing the STM32U535CBU6 datasheet, STM32U535CBU6 pinout, STM32U535CBU6 application, or STM32U535CBU6 equivalent, key selection criteria include TrustZone-enabled secure boot, LPBAM autonomous peripheral operation in Stop 2, 14-bit 2.5-Msps ADC with hardware oversampling, CAN FD interface, and UFQFPN48 package compatibility with space-constrained PCB layouts.
Technical Context
The device implements a dual-bank flash architecture enabling read-while-write and 100 kcycle endurance, paired with ART Accelerator featuring 8-Kbyte instruction cache and 4-Kbyte data cache for zero-wait-state execution at up to 160 MHz. Its power architecture integrates both LDO and SMPS with on-the-fly voltage scaling to optimize dynamic efficiency.
TrustZone security enforces hardware-isolated secure/non-secure worlds via SAU configuration and GTZC peripherals, supporting secure firmware installation (SFI) and TF-M-based over-the-air updates. The low-power design includes LPBAM mode-enabling DMA-driven peripheral chains without CPU wake-up-and VBAT-supplied RTC with 32×32-bit backup registers and 2-Kbyte backup SRAM.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | Arm Cortex-M33 with TrustZone, FPU, MPU, DSP extensions - enables secure real-time control with cryptographic acceleration and memory isolation. |
| Max Clock / Performance | 160 MHz / 240 DMIPS - supports high-throughput sensor fusion and protocol stacks without external co-processors. |
| Flash Memory | 512 KB with ECC, dual-bank, 100 kcycles - allows safe firmware updates with rollback protection and error correction in mission-critical deployments. |
| SRAM | 274 KB total, including 64 KB with ECC - provides robust data buffering for secure crypto operations and real-time analytics. |
| Low-Power Modes | 90 nA Shutdown, 370 nA Standby+RTC, 3.0 µA Stop 2 (16 KB SRAM retained) - extends battery life to years in wireless sensor nodes. |
| Analog Peripherals | 14-bit 2.5-Msps ADC (oversampling), 2×12-bit DAC, OPAMP with PGA, ultra-low-power comparator - enables precision analog front-end integration without external signal conditioning. |
| Connectivity | CAN FD, USB FS host/device, 5×USART/LPUART, 4×I²C FM+, SAI, SDMMC, OCTOSPI - supports mixed wired/wireless edge gateway architectures. |
Pinout & Package
STM32U535CBU6 is housed in a 48-pin UFQFPN (7 × 7 mm, 0.5 mm pitch) package, optimized for compact industrial and wearable designs. Pin functions support flexible I/O mapping with up to 82 fast GPIOs (most 5V-tolerant), independent supply for 14 I/Os down to 1.08 V, and dedicated TrustZone-secured pins for tamper detection and secure debug disable.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VSS | Main power supply and ground | Supports dual-supply operation with SMPS/LDO coexistence; decoupling required per datasheet layout guidelines. |
| VBAT | Backup power domain input | Supplies RTC, 32×32-bit backup registers, and 2-Kbyte backup SRAM during main power loss. |
| NRST | Active-low reset input | Asynchronous reset with internal pull-up; compatible with external reset supervisors and push-button recovery. |
| PA0–PA15, PB0–PB15, etc. | General-purpose I/Os | Up to 82 pins configurable as GPIO, alternate function, or analog; most tolerate 5 V even when VDD = 1.8 V. |
| PC13–PC15 | RTC oscillator inputs | Support 32.768 kHz crystal for calendar-grade timekeeping with hardware calibration and compensation. |
| PF0–PF1 | System clock inputs | Accept 4–50 MHz crystal or external clock source; feed RCC PLL for system clock generation up to 160 MHz. |
Key Features
| Feature | Design Value |
|---|---|
| LPBAM (Low-Power Background-Autonomous Mode) | Enables DMA-driven peripheral sequences (e.g., ADC→DMA→memory→trigger) while CPU remains in Stop 2 - eliminates wake-up latency and reduces active current by >90%. |
| FlexPowerControl with SMPS | Integrated step-down converter supports dynamic voltage scaling between 0.9 V and 1.2 V core supply - cuts active-mode power by up to 40% vs. LDO-only operation. |
| CORDIC + FMAC co-processors | Hardware-accelerated trigonometric and filter math offloads CPU during motor control or audio preprocessing - improves deterministic response and lowers firmware complexity. |
| Secure Root of Trust | Unique boot entry, HDP (Hide Protection Area), and embedded RSS (Root-Secure Services) enable certified secure boot and attestation - meets PSA Level 3 and SESIP requirements. |
| Ultra-Low-Power Analog Suite | 14-bit ADC with 2.5-Msps sampling and hardware oversampling, plus OPAMP with programmable gain amplifier - achieves ±0.5 LSB INL and <1 µV/°C offset drift for precision measurement without calibration. |
Applications
| Industrial Sensor Node | Secure Smart Meter |
|---|---|
Use Scenario: Battery-powered vibration and temperature monitoring in predictive maintenance systems deployed in remote substations. IC Role / Device Role / Timing Role: Main controller executing sensor fusion, secure OTA updates, and LPBAM-triggered ADC acquisition synchronized to mechanical events. Use Value: 3.0 µA Stop 2 mode with 16-Kbyte SRAM retention enables multi-year operation on coin-cell batteries; TrustZone isolates metering firmware from communication stack. | Use Scenario: ANSI C12.22-compliant electricity meter with tamper detection, encrypted billing data, and dual-band PLC/radio communication. IC Role / Device Role / Timing Role: Secure system-on-chip managing metrology ADC, HDP-protected tariff tables, and CAN FD backhaul to concentrator. Use Value: 96-bit unique ID and 512-byte OTP enable cryptographic key binding; VBAT-backed RTC ensures accurate time-of-use billing during grid outages. |
| Wearable Health Monitor | Wireless Gateway Controller |
Use Scenario: CE-certified ECG patch with dry-electrode sensing, motion artifact cancellation, and Bluetooth LE telemetry. IC Role / Device Role / Timing Role: Real-time signal processor using CORDIC for QRS detection and FMAC for adaptive filtering, with secure storage of PII in ECC SRAM. Use Value: 14-bit ADC oversampling achieves >100 dB SNR for sub-microvolt biopotential capture; LPBAM automates sensor wake-up without CPU intervention. | Use Scenario: LoRaWAN-to-Ethernet bridge aggregating data from 50+ field devices in smart agriculture deployments. IC Role / Device Role / Timing Role: Protocol translation hub running FreeRTOS, managing SDMMC logging, USB host for firmware updates, and CAN FD fieldbus interface. Use Value: Dual-bank flash enables atomic firmware swaps; OCTOSPI interface supports external XIP code execution to extend effective memory footprint. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32U575ZIT6 | Higher flash (2 MB), larger package (LQFP144), adds Ethernet MAC and JPEG codec - no UFQFPN48 option. | Suitable for gateway-class devices requiring rich connectivity and multimedia processing. | Select when needing >512 KB flash or Ethernet; avoid if board space or cost constraints favor 48-pin footprint. |
| RA4M3G10FB | Arm Cortex-M4F, 1 MB flash, 384 KB SRAM, no TrustZone, Renesas Secure Crypto Engine instead of PSA-certified TZ. | Targeted at industrial HMI and motor control where deterministic FPU performance outweighs PSA-level security. | Choose for legacy Renesas ecosystem compatibility or when SHA-256/AES acceleration suffices without full TrustZone isolation. |
Compared with STM32U535CBU6, the STM32U575ZIT6 offers greater memory and peripheral density but sacrifices compact packaging and cost efficiency, while the RA4M3G10FB trades PSA-certified security for higher FPU throughput and simpler certification paths in non-regulated environments.
Availability
STM32U535CBU6 is available at Aetrix Electronics and suitable for industrial sensor nodes, secure smart meters, wearable health monitors, and wireless gateway controllers requiring stable component supply across extended product lifecycles.
Supply support for STM32U535CBU6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, delivering silicon solutions for automotive, industrial, and consumer markets with emphasis on energy efficiency and security.
The STM32U5 series targets ultra-low-power, security-critical edge applications - combining Arm TrustZone with ST's proprietary FlexPowerControl and LPBAM to minimize energy-per-inference in battery-operated IoT endpoints.
FAQ
What is the maximum operating temperature rating for STM32U535CBU6?
The STM32U535CBU6 is qualified for operation from –40 °C to +125 °C ambient temperature, meeting industrial-grade thermal specifications. This rating applies to all package variants including the UFQFPN48, and is validated per JEDEC JESD22-A104 and JESD22-A108 reliability standards.
Does STM32U535CBU6 support hardware-accelerated cryptography?
Yes - it includes a HASH hardware accelerator supporting SHA-1, SHA-224, and SHA-256, plus a NIST SP800-90B-compliant true random number generator (TRNG). These blocks operate independently of the CPU and are accessible from both secure and non-secure worlds under TrustZone policy control.
Can the internal SMPS be used alongside the LDO simultaneously?
Yes - the SMPS and LDO can operate concurrently: SMPS supplies VCORE while LDO powers VDDIO2 and other I/O domains. Voltage scaling is managed dynamically via the PWR controller, and switching between regulators occurs without system reset, enabling seamless transition between high-performance and ultra-low-power modes.
Is the 14-bit ADC usable in Stop 2 mode?
No - the 14-bit ADC1 requires the APB bus clock and cannot operate in Stop 2. However, the 12-bit ADC4 is fully autonomous in Stop 2 mode and supports hardware oversampling, achieving up to 16-bit effective resolution while consuming only 1.2 µA during conversion sequences triggered by LPBAM.
STM32U535CBU6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 48-UFQFN Exposed Pad
- Series:
- STM32U5
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 160MHz
- Connectivity:
- CANbus, I2C, IrDA, LINbus, SAI, SmartCard, SPDIF, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
- Number of I/O:
- 37
- Program Memory Size:
- 128KB (128K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 274K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 11x12/14b SAR; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32U535CBU6 FAQ
1.How can I place an order for STM32U535CBU6 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32U535CBU6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32U535CBU6 reliable?
The price and inventory of STM32U535CBU6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32U535CBU6 is usually 5 days.
3.What payment methods are accepted for STM32U535CBU6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32U535CBU6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32U535CBU6?
STM32U535CBU6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32U535CBU6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32U535CBU6?
For technical support, including STM32U535CBU6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32U535CBU6 requirements.
6.How does Aetrix verify that STM32U535CBU6 is sourced from the original manufacturer or authorized distributors?
All STM32U535CBU6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32U535CBU6 meets industry standards.
7.What is the process for return or replacement of STM32U535CBU6?
All STM32U535CBU6 units undergo pre-shipment inspection (PSI). If there is an issue with STM32U535CBU6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32U535CBU6 part is unused and in its original packaging.
Return procedure for STM32U535CBU6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32U535CBU6 Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
