STMicroelectronics STM32U535CEU6
- Part No.:
- STM32U535CEU6
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 48-UFQFN Exposed Pad
- Datasheet:
-
STM32U535CEU6.pdf
- Description:
- IC MCU 32BIT 512KB FLSH 48UFQFPN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
STM32U535CEU6 from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 microcontroller with TrustZone® security, 512 KB flash, 274 KB SRAM, and integrated FPU-designed for secure, battery-operated edge nodes in industrial sensing and medical wearables. It delivers 240 DMIPS at up to 160 MHz, supports LPBAM autonomous peripheral operation down to Stop 2 mode, and features hardware-accelerated CORDIC/FMAC for real-time signal processing.
For engineers reviewing the STM32U535CEU6 datasheet, STM32U535CEU6 pinout, STM32U535CEU6 application, or STM32U535CEU6 equivalent, key selection criteria include its 90 nA Shutdown mode, dual 14-bit/12-bit ADCs with Stop 2 autonomy, TrustZone-enforced secure boot and memory isolation, and CAN FD + USB FS + Octo-SPI interface concurrency.
Technical Context
The STM32U535CEU6 implements a dual-bank flash architecture with ECC and read-while-write capability, enabling seamless firmware updates without halting execution. Its ART Accelerator includes 8-KB instruction cache and 4-KB data cache, allowing zero-wait-state execution from flash at 160 MHz and efficient access to external memories via Octo-SPI.
Power management integrates both LDO and SMPS step-down converters with dynamic voltage scaling and on-the-fly switching-critical for optimizing energy per compute cycle across Run, Stop 2, and Standby modes. The low-power background-autonomous mode (LPBAM) enables DMA-driven peripheral chains (e.g., ADC→DMA→CORDIC→SRAM) without CPU intervention, even in Stop 2.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone, FPU, MPU, and DSP extensions-enables secure, deterministic real-time control with cryptographic acceleration. |
| Max Clock / Performance | 160 MHz / 240 DMIPS-supports high-throughput sensor fusion and audio preprocessing in resource-constrained devices. |
| Memory | 512 KB flash (ECC, 2 banks, RWW), 274 KB SRAM (up to 64 KB with ECC)-provides robust code storage and large buffer space for secure OTA updates and multi-channel data buffering. |
| Low-Power Modes | 90 nA Shutdown, 370 nA Standby+RTC, 1.4 µA Stop 3 (16 KB SRAM)-enables >10-year battery life in coin-cell-powered IoT endpoints. |
| Analog Peripherals | 14-bit 2.5-Msps ADC (hardware oversampling), dual 12-bit DAC, OPAMP with PGA, ultra-low-power comparator-supports precision analog front-end design without external signal conditioning. |
| Security | TrustZone-enabled memory/peripheral isolation, 96-bit unique ID, 512-byte OTP, HASH accelerator, NIST SP800-90B TRNG-meets PSA Level 3 and SESIP certification prerequisites. |
| Connectivity | CAN FD, USB Full-Speed (host/device), 5x USART/LPUART, 4x I²C FM+, 3x SPI, SAI, SDMMC, Octo-SPI-enables mixed wired/wireless gateway architectures with legacy bus support. |
Pinout & Package
STM32U535CEU6 is housed in a 48-pin UFQFPN package (7 × 7 mm, 0.5 mm pitch), optimized for compact PCB layouts in space-constrained portable designs. Pin mapping aligns with STM32U5 series standardization for migration flexibility across density variants.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VDDIO2 | Core, analog, and I/O power supplies | Independent 1.71–3.6 V domains enable precise analog measurement and 5V-tolerant I/O interfacing simultaneously. |
| VSS, VSSA | Digital and analog ground returns | Separate analog/digital ground pins minimize noise coupling into ADC/DAC paths. |
| PA0–PA15, PB0–PB15, PC0–PC15, PD0–PD15, PE0–PE15 | General-purpose I/Os | Up to 82 fast I/Os with interrupt capability; 14 support independent 1.08–3.6 V supply for mixed-voltage system interfacing. |
| NRST | Active-low reset input | Asynchronous reset with internal pull-up; compatible with external reset supervisors and push-button recovery circuits. |
| BOOT0 | Boot mode selection | Configures boot source (system memory, embedded flash, or SRAM); critical for secure bootloader initialization and field recovery. |
| PA13/PA14 | SWD debug interface | Serial Wire Debug (SWD) pins-support full-speed programming, trace, and real-time debugging without JTAG overhead. |
| PA9/PA10 | USB_FS_DM/DP | Differential USB Full-Speed transceiver interface-enables HID, CDC, or DFU class implementations without external PHY. |
| PD0/PD1 | OSC_IN/OSC_OUT | 4–50 MHz crystal oscillator inputs-supports high-accuracy timing for RTC, USB, and communication protocols. |
Key Features
| Feature | Design Value |
|---|---|
| LPBAM (Low-Power Background-Autonomous Mode) | Enables DMA-chained peripheral operation (e.g., ADC→CORDIC→SRAM) in Stop 2 mode-eliminates CPU wake-ups and reduces active time by >90% in sensor logging applications. |
| FlexPowerControl with SMPS + LDO | Dynamic switching between SMPS (high efficiency) and LDO (low noise) based on operating mode-optimizes power delivery for both RF-sensitive analog sections and high-speed digital logic. |
| TrustZone + GTZC (Global TrustZone Controller) | Hardware-enforced separation of secure/non-secure firmware, peripherals, and memory regions-required for PSA Certified Level 3 and secure element coexistence. |
| CORDIC + FMAC Co-processors | Accelerates trigonometric, hyperbolic, and filtering operations in <100 cycles-reduces CPU load for motor control, FFT-based spectral analysis, and adaptive filtering in real-time. |
| VBAT Domain with RTC + Backup SRAM | Retains calendar time, 32×32-bit registers, and 2 KB SRAM during main power loss-enables tamper-proof timestamping and state preservation in security-critical systems. |
Applications
| Industrial Predictive Maintenance Sensor | Portable Medical ECG Monitor |
|---|---|
Use Scenario: Vibration and temperature monitoring on rotating machinery using MEMS accelerometers and thermistors. IC Role / Device Role / Timing Role: MCU executes LPBAM-triggered ADC sampling, CORDIC-based FFT feature extraction, and secure BLE packet formatting-all while maintaining <2 µA average current draw. Use Value: Enables 5-year battery life with continuous monitoring and encrypted anomaly reporting to cloud platforms. | Use Scenario: Single-lead ECG acquisition with motion artifact suppression and real-time arrhythmia detection. IC Role / Device Role / Timing Role: Manages ultra-low-noise analog front-end (OPAMP + 14-bit ADC), runs adaptive digital filters on FMAC, and stores waveform snippets in ECC-protected SRAM during brief wake periods. Use Value: Achieves clinical-grade signal fidelity while meeting IEC 60601-1 leakage current limits and FDA cybersecurity guidance. |
| Smart Utility Meter (Gas/Water) | Secure Asset Tracking Beacon |
Use Scenario: Ultrasonic flow measurement with pulse transit time calculation and LoRaWAN telemetry transmission. IC Role / Device Role / Timing Role: Controls precision timing capture via advanced timers, performs time-of-flight math on CORDIC, and secures firmware updates via TF-M-compliant secure boot. Use Value: Delivers ±0.5% flow accuracy over 15-year deployment with anti-tamper RTC logging and remote attestation. | Use Scenario: GPS-denied indoor location tracking using UWB anchor synchronization and encrypted Bluetooth LE advertising. IC Role / Device Role / Timing Role: Orchestrates ultra-precise time-of-arrival measurements via LPTIMs, validates anchor identities using HASH/ECDSA, and maintains secure session keys in TrustZone-protected RAM. Use Value: Provides sub-meter indoor positioning with end-to-end encryption and zero-trust device identity binding. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32U575ZIT6 | Higher flash (2 MB) and SRAM (1 MB), adds Ethernet MAC and crypto accelerator; 144-pin LQFP144 package. | Suitable for gateway-class devices requiring TLS offload and network bridging-not optimized for sub-µA endpoint sleep. | Select when needing >1 MB code space, hardware TLS, or wired connectivity; avoid for size/power-constrained sensors. |
| RA4M3G20CBH#AC0 | Arm Cortex-M4F core, 1 MB flash, 384 KB SRAM, no TrustZone; Renesas Secure Crypto Engine instead of PSA-certified TZ. | Lacks LPBAM and sub-100 nA shutdown; higher active power (2.1 µA/MHz vs. 1.4 µA/MHz). | Consider only if existing Renesas toolchain investment outweighs security/ultra-low-power trade-offs. |
Compared with STM32U575ZIT6 and RA4M3G20CBH#AC0, the STM32U535CEU6 uniquely balances sub-100 nA shutdown, TrustZone-certified security, and LPBAM-driven autonomous processing-making it optimal for long-life, certifiable, sensor-edge deployments where every nanoamp and security boundary matters.
Availability
STM32U535CEU6 is available at Aetrix Electronics and suitable for industrial predictive maintenance sensors, portable medical monitors, smart utility meters, and secure asset tracking beacons requiring stable component supply across multi-year production cycles.
Supply support for STM32U535CEU6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, delivering silicon solutions for automotive, industrial, and consumer markets since 1987.
The STM32U5 series is ST's flagship ultra-low-power secure MCU product line, engineered specifically for PSA Certified Level 3 and SESIP-certified IoT endpoints demanding sub-100 nA shutdown, hardware-isolated security, and autonomous peripheral processing.
FAQ
What is the maximum operating temperature range for the STM32U535CEU6?
The STM32U535CEU6 is rated for operation from –40 °C to +125 °C ambient temperature, validated per JEDEC JESD22-A104. This extended range supports deployment in harsh industrial environments such as motor drives, smart grid infrastructure, and automotive under-hood telemetry modules where thermal stability is critical.
Does the STM32U535CEU6 support hardware-accelerated AES encryption?
No-the STM32U535CEU6 does not integrate a dedicated AES engine. Security acceleration relies on its TrustZone-enforced software execution environment, HASH hardware accelerator (SHA-1/SHA-224/SHA-256), and NIST SP800-90B compliant TRNG. AES operations must be implemented in firmware using optimized libraries running in secure world.
Can the STM32U535CEU6 run FreeRTOS in the secure world with TF-M?
Yes-TF-M (Trusted Firmware-M) provides the secure kernel and IPC layer, while FreeRTOS can be deployed in the non-secure world. The GTZC enforces strict memory and peripheral isolation between worlds, and the dual-bank flash supports atomic firmware updates verified by the secure boot ROM before handoff to TF-M.
What is the minimum supply voltage required for the VDDIO2 domain?
The VDDIO2 domain supports voltages from 1.08 V to 3.6 V, enabling direct interfacing with low-voltage peripherals like 1.2 V or 1.8 V sensors and memories. This independent I/O rail allows mixed-signal system integration without level shifters, reducing BOM cost and PCB area in battery-powered designs.
STM32U535CEU6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 48-UFQFN Exposed Pad
- Series:
- STM32U5
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 160MHz
- Connectivity:
- CANbus, I2C, IrDA, LINbus, SAI, SmartCard, SPDIF, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
- Number of I/O:
- 37
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 274K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 11x12/14b SAR; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32U535CEU6 FAQ
1.How can I place an order for STM32U535CEU6 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32U535CEU6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32U535CEU6 reliable?
The price and inventory of STM32U535CEU6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32U535CEU6 is usually 5 days.
3.What payment methods are accepted for STM32U535CEU6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32U535CEU6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32U535CEU6?
STM32U535CEU6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32U535CEU6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32U535CEU6?
For technical support, including STM32U535CEU6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32U535CEU6 requirements.
6.How does Aetrix verify that STM32U535CEU6 is sourced from the original manufacturer or authorized distributors?
All STM32U535CEU6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32U535CEU6 meets industry standards.
7.What is the process for return or replacement of STM32U535CEU6?
All STM32U535CEU6 units undergo pre-shipment inspection (PSI). If there is an issue with STM32U535CEU6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32U535CEU6 part is unused and in its original packaging.
Return procedure for STM32U535CEU6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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