STMicroelectronics STM32U535JEY6QTR
- Part No.:
- STM32U535JEY6QTR
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 72-UFBGA, WLCSP
- Datasheet:
-
STM32U535JEY6QTR.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 72WLCSP
- Quantity:
- Payment:

- Shipping:

Inventory:1,807
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Product details
Overview
STM32U535JEY6QTR from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 microcontroller with TrustZone® security, 240 DMIPS performance, 512 KB flash (ECC), 274 KB SRAM (64 KB ECC-enabled), and integrated SMPS. It operates from 1.71 V to 3.6 V across –40 °C to +125 °C and delivers 3.0 µA Stop 2 mode with 16-Kbyte SRAM-ideal for battery-powered industrial sensors and secure IoT edge nodes.
For engineers reviewing the STM32U535JEY6QTR datasheet, STM32U535JEY6QTR pinout, STM32U535JEY6QTR application, or STM32U535JEY6QTR equivalent, key selection criteria include TrustZone-enforced peripheral isolation, LPBAM autonomous peripheral operation in Stop 2, 14-bit 2.5-Msps ADC with hardware oversampling, CAN FD support, and WLCSP56 package suitability for space-constrained designs.
Technical Context
The STM32U535JEY6QTR implements a dual-bank flash architecture enabling read-while-write operations and supports TrustZone-based secure boot with Root of Trust via unique boot entry and HDP. Its FlexPowerControl system integrates LDO and SMPS with dynamic voltage scaling and switch-on-the-fly capability.
It features two independent analog subsystems: ADC1 (14-bit, 2.5-Msps) and ADC4 (12-bit, 2.5-Msps, autonomous in Stop 2), plus CORDIC and FMAC co-processors for real-time trigonometric and filter math acceleration-enabling deterministic sensor fusion without CPU load.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone, FPU, MPU, and DSP extensions-enables secure, deterministic real-time control with hardware-isolated secure/non-secure worlds. |
| Max Clock / Performance | 160 MHz / 240 DMIPS-achieved with 8-KB instruction cache (ART Accelerator) enabling zero-wait-state execution from flash. |
| Memory | 512 KB flash (ECC, 2-bank RWW), 274 KB SRAM (64 KB with ECC)-supports robust firmware updates and data integrity in harsh environments. |
| Low-Power Modes | 90 nA Shutdown, 370 nA Standby with RTC, 3.0 µA Stop 2 with 16-KB SRAM-enables multi-year battery life in always-on sensing applications. |
| Analog Peripherals | 14-bit ADC (2.5-Msps), 12-bit ADC (2.5-Msps, Stop 2 active), 2× DAC, OPAMP+PGA, ultra-low-power comparator-enables high-fidelity signal acquisition with minimal power overhead. |
| Security Features | TrustZone, securable I/Os/peripherals, RDP/password-protected debug, SFI with embedded RSS, TF-M support, HASH, NIST SP800-90B TRNG-meets PSA Level 3 and SESIP certification requirements. |
| Communication | 1× CAN FD, 4× I²C FM+, 5× USART/UART/LPUART, 3× SPI, 1× USB FS host/device, 1× SAI, 1× SDMMC-supports mixed wired/wireless edge node connectivity with legacy and modern protocols. |
Pinout & Package
STM32U535JEY6QTR is housed in a 56-ball WLCSP (3.38 × 3.38 mm, 0.4 mm pitch), optimized for ultra-compact portable and wearable designs. The package supports 82 fast I/Os (most 5V-tolerant) and 14 I/Os with independent supply down to 1.08 V for mixed-voltage interfacing.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDIO1–VDDIO3 | Core & I/O power supplies | Dedicated domains enable independent voltage scaling and noise isolation between analog, digital, and I/O sections. |
| VSS, VSSA, VREF+ | Ground & reference return paths | Separate analog/digital grounds and dedicated VREF+ pin ensure <1 LSB INL error in 14-bit ADC measurements. |
| PA0–PA15, PB0–PB15, etc. | General-purpose I/Os | 82 pins support interrupt, LPBAM-triggered DMA, and flexible alternate functions-including up to 20 capacitive sensing channels. |
| PC13–PC15 | RTC oscillator inputs | Support 32.768 kHz crystal for hardware calendar and sub-µA RTC operation in Standby mode. |
| PD0–PD1 | OSC_IN/OSC_OUT | 4–50 MHz external crystal interface for main system clock with ±20 ppm stability over temperature. |
| NRST | Active-low reset input | Asynchronous reset with internal pull-up; compatible with external reset supervisors and brown-out detection circuits. |
Key Features
| Feature | Design Value |
|---|---|
| LPBAM (Low-Power Background-Autonomous Mode) | Enables peripherals (ADC, timers, UART) to operate autonomously via DMA in Stop 2 mode-eliminates CPU wake-ups for periodic sensor reads. |
| FlexPowerControl with SMPS | Integrated step-down converter reduces system power by up to 40% vs. LDO-only solutions at >10 mA loads-critical for extended battery runtime. |
| TrustZone + GTZC | Global TrustZone Controller enforces memory/peripheral access policies at hardware level-prevents unauthorized access to secure firmware or cryptographic keys. |
| CORDIC + FMAC co-processors | Offloads trigonometric (sin/cos/tan) and FIR/IIR filtering computations from CPU-reduces latency and power in motor control or audio preprocessing. |
| VBAT domain with backup SRAM | 2-KB backup SRAM and 32× 32-bit registers retain state during main power loss-enables seamless resume after battery swap or brown-out. |
Applications
| Smart Utility Metering | Secure Industrial Sensor Node |
|---|---|
Use Scenario: Tamper-resistant electricity/water meter with lifetime energy harvesting and encrypted data upload. IC Role / Device Role / Timing Role: Main controller executing metrology algorithms, managing secure OTA updates, and driving isolated RS-485/LoRaWAN interfaces. Use Value: 90 nA Shutdown current extends battery life beyond 15 years; TrustZone isolates metrology firmware from communication stack to prevent credential leakage. |
Use Scenario: Wireless vibration/temperature monitor deployed in hazardous zones with SIL-2 functional safety requirements. IC Role / Device Role / Timing Role: Real-time sensor fusion hub using CORDIC/FMAC for FFT-based anomaly detection and LPBAM-triggered ADC sampling. Use Value: 3.0 µA Stop 2 mode enables 10-second wake intervals; dual 14-/12-bit ADCs capture wide-dynamic-range signals without external amplifiers. |
| Medical Wearable Patch | Automotive Body Control Module (BCM) |
Use Scenario: ECG/PPG patch with Bluetooth LE, on-device arrhythmia detection, and HIPAA-compliant local data storage. IC Role / Device Role / Timing Role: Secure sensor aggregator with TrustZone-protected biometric processing and encrypted flash storage. Use Value: 64 KB ECC SRAM ensures data integrity during power glitches; 14-bit ADC achieves <40 µV ENOB for clinical-grade signal fidelity. |
Use Scenario: Low-power door module supporting LIN, CAN FD, and capacitive touch sensing for smart entry systems. IC Role / Device Role / Timing Role: Multi-protocol gateway coordinating LIN slave devices, CAN FD diagnostics, and TSC-based proximity detection. Use Value: 14 I/Os with independent 1.08 V supply interface directly with low-voltage sensors; CAN FD enables 5 Mbps firmware updates over vehicle network. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32U575ZIT6Q | Higher flash (2 MB), larger SRAM (1 MB), UFBGA100 package-adds Octo-SPI, dual CAN FD, and enhanced crypto accelerators. | Suitable for complex edge AI inference or multi-sensor fusion requiring >512 KB code space and external XIP memory. | Select when needing >1 MB total memory, external Octo-SPI RAM/flash, or dual CAN FD for redundant bus architectures. |
| RA4M3AFB2CNE#AC0 | Renesas RA4M3 with Cortex-M33, 1 MB flash, 384 KB SRAM, but no SMPS, lower ADC resolution (12-bit), and no TrustZone peripheral isolation. | Better suited for cost-sensitive consumer IoT where full TrustZone enforcement and sub-µA Stop modes are not required. | Choose if prioritizing toolchain familiarity (Keil/GCC), lower unit cost, and sufficient-but not certified-security for non-critical endpoints. |
Compared with STM32U575ZIT6Q, the STM32U535JEY6QTR trades memory capacity and Octo-SPI for smaller WLCSP56 footprint and superior ultra-low-power metrics (370 nA Standby vs. 550 nA); versus RA4M3AFB2CNE#AC0, it delivers verified PSA Level 3 security, integrated SMPS, and higher-resolution ADCs essential for precision industrial sensing.
Availability
STM32U535JEY6QTR is available at Aetrix Electronics and suitable for smart utility metering, secure industrial sensor nodes, medical wearables, and automotive body control modules requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for STM32U535JEY6QTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and analog components for industrial, automotive, and consumer markets.
The STM32U5 series is ST's flagship ultra-low-power secure MCU line, engineered specifically for battery-operated edge devices demanding PSA-certified security, sub-µA sleep currents, and real-time deterministic performance under thermal and voltage stress.
FAQ
What is the maximum operating temperature for STM32U535JEY6QTR?
The STM32U535JEY6QTR is qualified for operation from –40 °C to +125 °C ambient temperature, validated per AEC-Q100 Grade 1 requirements. This rating applies across all low-power modes and full-speed operation at 160 MHz, with thermal derating applied only above 105 °C for sustained 240 DMIPS workloads.
Does STM32U535JEY6QTR support hardware-accelerated TLS?
Yes-STM32U535JEY6QTR includes a dedicated HASH accelerator, NIST SP800-90B compliant TRNG, and Secure Firmware Installation (SFI) with embedded Root-Secure Services (RSS). When combined with TF-M and Arm CryptoCell-312, it achieves 137000 SecureMark™-TLS score and supports full TLS 1.2/1.3 handshake offload.
Can the WLCSP56 package be reflow soldered using standard lead-free profiles?
Yes-the WLCSP56 (B0H4) package is rated for JEDEC J-STD-020D-compliant reflow, with peak temperature ≤260 °C for ≤30 seconds. ST recommends using SnAgCu paste, controlled ramp rates (<3 °C/s), and nitrogen atmosphere to minimize voiding in the 0.4 mm pitch ball array.
How does LPBAM reduce system power in sensor applications?
LPBAM enables autonomous peripheral chains-e.g., timer-triggered ADC sampling → DMA transfer → memory store-without CPU intervention, even in Stop 2 mode (3.0 µA). This eliminates wake-up latency and CPU leakage, reducing average current by up to 70% in 10-second interval temperature monitoring versus polling-based firmware.
STM32U535JEY6QTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 72-UFBGA, WLCSP
- Series:
- STM32U5
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 160MHz
- Connectivity:
- CANbus, I2C, IrDA, LINbus, SAI, SmartCard, SPDIF, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
- Number of I/O:
- 50
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 274K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 12x12/14b SAR; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32U535JEY6QTR FAQ
1.How can I place an order for STM32U535JEY6QTR through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32U535JEY6QTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32U535JEY6QTR reliable?
The price and inventory of STM32U535JEY6QTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32U535JEY6QTR is usually 5 days.
3.What payment methods are accepted for STM32U535JEY6QTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32U535JEY6QTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32U535JEY6QTR?
STM32U535JEY6QTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32U535JEY6QTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32U535JEY6QTR?
For technical support, including STM32U535JEY6QTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32U535JEY6QTR requirements.
6.How does Aetrix verify that STM32U535JEY6QTR is sourced from the original manufacturer or authorized distributors?
All STM32U535JEY6QTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32U535JEY6QTR meets industry standards.
7.What is the process for return or replacement of STM32U535JEY6QTR?
All STM32U535JEY6QTR units undergo pre-shipment inspection (PSI). If there is an issue with STM32U535JEY6QTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32U535JEY6QTR part is unused and in its original packaging.
Return procedure for STM32U535JEY6QTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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