STMicroelectronics STM32U535RBT6
- Part No.:
- STM32U535RBT6
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 64-LQFP
- Datasheet:
-
STM32U535RBT6.pdf
- Description:
- IC MCU 32BIT 128KB FLASH 64LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:4,191
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Product details
Overview
STM32U535RBT6 from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 microcontroller with TrustZone® security, 512 KB flash, 274 KB SRAM, and integrated FPU-designed for secure, battery-powered edge nodes in industrial sensing and medical wearables. It delivers 240 DMIPS at up to 160 MHz, supports LPBAM autonomous peripheral operation down to Stop 2 mode, and features hardware accelerators including CORDIC and FMAC.
For engineers reviewing the STM32U535RBT6 datasheet, STM32U535RBT6 pinout, STM32U535RBT6 application, or STM32U535RBT6 equivalent, key selection criteria include its 90 nA Shutdown mode, dual 14-bit/12-bit ADCs with Stop 2 autonomy, CAN FD interface, TrustZone-enabled secure boot, and LQFP48 package compatibility with legacy STM32L4/L5 footprint constraints.
Technical Context
The STM32U535RBT6 implements a dual-bank flash architecture with ECC and read-while-write capability, enabling seamless firmware updates without halting execution. Its ART Accelerator includes 8-Kbyte instruction cache and 4-Kbyte data cache, allowing zero-wait-state execution from flash at 160 MHz and efficient access to external Octo-SPI memories.
Power management integrates both LDO and SMPS step-down converters with on-the-fly voltage scaling, supporting dynamic transition between Run (16.3 µA/MHz), Stop 2 (3.0 µA), and Shutdown (90 nA) modes. Security relies on Arm TrustZone®, securable I/Os/peripherals, Root of Trust via unique boot entry, and embedded Secure Firmware Installation (SFI) services.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone, FPU, MPU, and DSP extensions-enables secure real-time control with deterministic floating-point math. |
| Max Clock Speed | 160 MHz with 0-wait-state execution via 8-KB instruction cache-guarantees deterministic latency-critical timing in motor control or audio processing. |
| Memory | 512 KB flash (ECC, 2-bank RWW), 274 KB SRAM (up to 64 KB with ECC)-supports robust firmware resilience and large buffer handling for sensor fusion. |
| Low-Power Modes | 90 nA Shutdown, 200 nA Standby, 3.0 µA Stop 2 with 16 KB SRAM-extends battery life in multi-year IoT deployments without compromising wake-up responsiveness. |
| Analog Peripherals | 14-bit ADC @ 2.5 Msps + 12-bit ADC autonomous in Stop 2, 2× DAC, OPAMP with PGA, ultra-low-power comparator-enables high-fidelity signal acquisition during ultra-low-power sleep states. |
| Security Features | TrustZone isolation, 96-bit unique ID, 512-byte OTP, HASH accelerator, NIST SP800-90B TRNG, secure firmware upgrade via TF-M-meets PSA Certified Level 3 and IEC 62443 requirements. |
| Communication | CAN FD, USB FS host/device, 5× USART/LPUART, 4× I²C FM+, 3× SPI, SAI, SDMMC, OCTOSPI-supports mixed wired/wireless connectivity in constrained-edge gateways. |
Pinout & Package
LQFP48 (7 × 7 mm, 0.5 mm pitch) package with exposed thermal pad; RoHS-compliant, ECOPACK2 certified. Pin count: 48 leads, including 37 general-purpose I/Os (most 5V-tolerant), VDD/VSS power rails, VBAT, VREF+, VREF–, and dedicated debug (SWDIO/SWCLK) and reset (NRST) pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PA0–PA15, PB0–PB15, PC0–PC15, PD0–PD15, PE0–PE15 | General-purpose I/Os | Up to 37 fast GPIOs with interrupt capability; most tolerate 5 V-simplifies level-shifting in mixed-voltage systems. |
| VDD, VSS | Core power supply | 1.71–3.6 V main supply; supports direct connection to Li-ion or coin-cell sources with internal regulator bypass options. |
| VBAT | Backup domain supply | Powers RTC, 32×32-bit backup registers, and 2 KB backup SRAM during main power loss-enables timekeeping and state retention in energy-harvesting designs. |
| NRST | Active-low reset input | Asynchronous reset pin with internal pull-up; compatible with external push-button or supervisor ICs for system-level fault recovery. |
| SWDIO / SWCLK | Debug interface | 2-pin Serial Wire Debug (SWD) interface-enables full programming, tracing, and real-time debugging without JTAG overhead. |
Key Features
| Feature | Design Value |
|---|---|
| LPBAM (Low-Power Background Autonomous Mode) | Enables DMA-driven peripheral chains (e.g., ADC→DMA→memory) without CPU involvement-reduces active time by >90% in sensor logging applications. |
| FlexPowerControl with SMPS+LDO | Dual-regulator system allows dynamic switching between SMPS (high-efficiency) and LDO (low-noise) based on operating mode-optimizes PSRR and quiescent current simultaneously. |
| CORDIC + FMAC co-processors | Hardware-accelerated trigonometric and filtering operations-cuts CPU load by ~70% in motor control FOC or biomedical FFT preprocessing. |
| Secure Boot with HDP & RDP | Root-secure boot using hidden protection area (HDP) and configurable read-out protection (RDP)-prevents firmware extraction and unauthorized debug access in field-deployed devices. |
| Octo-SPI Interface | Single 8-line interface supporting XIP (execute-in-place) from external NOR/NAND/DRAM-eliminates need for external RAM in code-intensive applications like OTA update staging. |
Applications
| Industrial Predictive Maintenance Sensor | Portable Medical ECG Monitor |
|---|---|
Use Scenario: Wireless vibration and temperature node mounted on rotating machinery, transmitting anomaly alerts every 15 minutes via LoRaWAN. IC Role / Device Role / Timing Role: Main controller executing sensor fusion (ADC + OPAMP + CORDIC), managing LPBAM-triggered sampling, and securing telemetry with TLS via HASH+TRNG. Use Value: 90 nA Shutdown current extends 2xAA battery life beyond 5 years; Stop 2 mode with autonomous ADC enables precise 10 kHz sampling bursts without waking CPU. | Use Scenario: Wearable patch capturing 3-lead ECG signals, performing real-time QRS detection, and storing encrypted waveform snippets locally. IC Role / Device Role / Timing Role: Secure signal processor running TrustZone-isolated firmware, driving 14-bit ADC at 2.5 Msps with hardware oversampling, and managing BLE transmission via LPUART. Use Value: 12-bit ADC operational in Stop 2 mode captures baseline biopotentials during low-power sleep; 2 KB backup SRAM retains last 30 seconds of raw data across resets. |
| Smart Building Occupancy Controller | Energy-Harvesting Wireless Valve Actuator |
Use Scenario: Battery-free occupancy detector using PIR + ambient light + ultrasonic sensing, powered by indoor solar cell and supercapacitor. IC Role / Device Role / Timing Role: Ultra-low-power coordinator managing multi-sensor fusion, event-triggered wake-up, and Zigbee stack execution via SAI and UART. Use Value: 370 nA Standby with RTC ensures accurate time-of-day scheduling; 14-channel capacitive sensing replaces mechanical switches with touchless UI. | Use Scenario: Self-powered HVAC valve actuator harvesting energy from pipe vibration, storing charge in 100 mF capacitor, and actuating only on command. IC Role / Device Role / Timing Role: Energy-aware actuation manager using CAN FD for fieldbus communication, controlling H-bridge via advanced timers, and monitoring battery voltage via VBAT channel. Use Value: 4.6 µA Stop 2 mode with full SRAM preserves valve position and calibration data during multi-hour energy harvest cycles; CAN FD enables deterministic 2 Mbps command delivery in noisy plant environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32L562RET6 | Same Cortex-M33 core and TrustZone, but 512 KB flash / 256 KB SRAM, no CORDIC/FMAC, lower ULPMark-CP (380 vs 464) | Lacks hardware math acceleration and Octo-SPI; suitable for simpler secure boot + BLE gateway roles without intensive signal processing | Select when cost sensitivity outweighs need for analog compute acceleration and external memory expansion. |
| RA4M3GDB001#AC0 | Arm Cortex-M33, 1 MB flash / 384 KB SRAM, no TrustZone, Renesas Secure Crypto Engine instead of full TrustZone, no LPBAM | Higher memory capacity but lacks autonomous peripheral chaining; security relies on software-managed crypto engine rather than hardware-isolated domains | Prefer for high-memory data concentrators where deterministic low-power autonomy is secondary to local encryption throughput. |
Compared with STM32L562RET6, the STM32U535RBT6 adds CORDIC/FMAC for real-time signal math and Octo-SPI for external code storage; versus RA4M3GDB001#AC0, it provides hardware-enforced TrustZone isolation and LPBAM-critical for certified medical or industrial safety functions requiring runtime domain separation.
Availability
STM32U535RBT6 is available at Aetrix Electronics and suitable for industrial predictive maintenance sensors, portable medical monitors, smart building controllers, and energy-harvesting actuators requiring stable component supply across long-lifecycle deployments.
Supply support for STM32U535RBT6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, delivering silicon solutions for automotive, industrial, and consumer markets since 1987.
The STM32U5 series targets ultra-low-power, secure edge intelligence-designed specifically for battery-constrained, safety-certifiable applications where runtime autonomy, cryptographic integrity, and sub-µA sleep currents are non-negotiable.
FAQ
What is the maximum operating temperature range for STM32U535RBT6?
The STM32U535RBT6 is qualified for industrial operation from –40 °C to +85 °C and extended industrial operation up to +125 °C. This rating applies to all LQFP48 variants per DS14217 Rev 5 Section 5.3.1, validated under JEDEC JESD47 stress conditions with full functionality across the range.
Does STM32U535RBT6 support USB device and host modes simultaneously?
No. The integrated USB full-speed controller supports either device or host mode-not simultaneous dual-role operation. Mode selection is configured at initialization via the USB_OTG_FS_GOTGCTL register; switching requires reinitialization and is not hot-swappable per Section 3.44 of the datasheet.
How many wake-up pins are available in Shutdown mode?
The STM32U535RBT6 provides 23 dedicated wake-up pins in Shutdown mode, all capable of generating interrupts from deep sleep. These include all GPIOs except those multiplexed exclusively for analog functions (e.g., VREF+, VREF–) and are documented in Table 13 of DS14217 Rev 5 Section 4.2.
Is the 512-byte OTP memory one-time programmable or field-reprogrammable?
The 512-byte OTP (one-time programmable) memory is permanently write-once: bits can be programmed from '1' to '0', but cannot be reverted. It is used for critical keys, calibration data, or device-specific identifiers and is accessible only in secure privileged mode after TrustZone initialization per Section 3.7.2 and Table 10 of the datasheet.
STM32U535RBT6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 64-LQFP
- Series:
- STM32U5
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 160MHz
- Connectivity:
- CANbus, I2C, IrDA, LINbus, SAI, SmartCard, SPDIF, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
- Number of I/O:
- 51
- Program Memory Size:
- 128KB (128K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 274K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 17x12/14b SAR; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32U535RBT6 FAQ
1.How can I place an order for STM32U535RBT6 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32U535RBT6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32U535RBT6 reliable?
The price and inventory of STM32U535RBT6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32U535RBT6 is usually 5 days.
3.What payment methods are accepted for STM32U535RBT6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32U535RBT6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32U535RBT6?
STM32U535RBT6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32U535RBT6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32U535RBT6?
For technical support, including STM32U535RBT6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32U535RBT6 requirements.
6.How does Aetrix verify that STM32U535RBT6 is sourced from the original manufacturer or authorized distributors?
All STM32U535RBT6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32U535RBT6 meets industry standards.
7.What is the process for return or replacement of STM32U535RBT6?
All STM32U535RBT6 units undergo pre-shipment inspection (PSI). If there is an issue with STM32U535RBT6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32U535RBT6 part is unused and in its original packaging.
Return procedure for STM32U535RBT6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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