STMicroelectronics STM32U535RCI6Q
- Part No.:
- STM32U535RCI6Q
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 64-UFBGA
- Datasheet:
-
STM32U535RCI6Q.pdf
- Description:
- IC MCU 32BIT 256KB FLASH 64UFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
STM32U535RCI6Q from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 microcontroller with TrustZone® security, 512 KB flash, 274 KB SRAM, and integrated FPU/MPU-designed for battery-powered IoT edge nodes requiring secure firmware updates, real-time sensor fusion, and sub-μA standby operation. It delivers 240 DMIPS at 160 MHz, supports LPBAM autonomous peripheral operation down to Stop 2 mode, and integrates hardware accelerators including CORDIC, FMAC, HASH, and a NIST SP800-90B-compliant TRNG.
For engineers reviewing the STM32U535RCI6Q datasheet, STM32U535RCI6Q pinout, STM32U535RCI6Q application, or STM32U535RCI6Q equivalent, key selection criteria include TrustZone-enforced secure boot, 90 nA Shutdown mode with 23 wake-up pins, dual 14-/12-bit ADCs with hardware oversampling active in Stop 2, CAN FD interface, and Octo-SPI support for external memory expansion.
Technical Context
The STM32U535RCI6Q implements a dual-cache ART Accelerator (8 KB I-Cache + 4 KB D-Cache) enabling zero-wait-state execution from flash and external memories up to 160 MHz. Its power architecture combines embedded LDO and SMPS step-down converter with dynamic voltage scaling and on-the-fly switching for optimal efficiency across operating modes.
TrustZone security is implemented at silicon level with GTZC controller managing secure/non-secure memory partitioning, securable peripherals, and RDP-protected debug access. The device features two independent ADCs (14-bit @ 2.5 Msps and 12-bit @ 2.5 Msps), both operational in Stop 2 mode, plus dual DACs, OPAMP with PGA, and ultra-low-power comparator-all with independent supply domains.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone, FPU, MPU, and DSP extensions-enables secure real-time control with deterministic floating-point math. |
| Max Clock / Performance | 160 MHz / 240 DMIPS-supports high-throughput signal processing while maintaining sub-μA/MHz efficiency in Run mode. |
| Memory | 512 KB flash (ECC, RWW), 274 KB SRAM (up to 64 KB with ECC)-enables robust firmware storage and large buffer handling for sensor data aggregation. |
| Low-Power Modes | 90 nA Shutdown, 370 nA Standby+RTC, 1.4 μA Stop 3 (16 KB SRAM retained)-extends coin-cell battery life to multi-year deployments. |
| Analog Peripherals | 14-bit ADC @ 2.5 Msps + 12-bit ADC @ 2.5 Msps (both active in Stop 2), 2× DAC, OPAMP+PGA, comparator-supports simultaneous high-resolution sensing and analog conditioning without CPU wake-up. |
| Security Features | TrustZone, 96-bit UID, 512-byte OTP, Secure Firmware Installation (SFI), TF-M compatible, HASH accelerator, TRNG-meets PSA Level 3 and SESIP certification prerequisites. |
| Communication Interfaces | CAN FD, USB FS (host/device), 5× USART/LPUART, 4× I²C FM+, 3× SPI, SAI, SDMMC, Octo-SPI-enables mixed wired/wireless connectivity in constrained-edge gateways. |
Pinout & Package
LQFP64 (10 × 10 mm, 0.5 mm pitch) package with exposed thermal pad. Pin count: 64 leads. RoHS-compliant ECOPACK2 packaging.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VDDIO2 | Power supply inputs | Separate domains for core (1.71–3.6 V), analog (1.62–3.6 V), and I/O (1.08–3.6 V) enable precise noise isolation and flexible voltage scaling. |
| PA0–PA15, PB0–PB15, PC0–PC15, PD0–PD15, PE0–PE15 | General-purpose I/Os | Up to 82 fast I/Os; most 5V-tolerant, 14 with independent VDDIO2 supply down to 1.08 V-supports mixed-voltage system interfacing. |
| NRST | Active-low reset input | Asynchronous reset with internal pull-up; supports external reset supervision and tamper-triggered secure wipe. |
| BOOT0 | Boot mode selection | Configures boot source (system memory, flash, or SRAM); critical for secure OTA update fallback and factory recovery. |
| SWDIO / SWCLK | Serial Wire Debug interface | 2-pin debug port supporting full SWD protocol; TrustZone-secured access requires authenticated debug session. |
| VBAT | Backup power supply | Supplies RTC, 32×32-bit backup registers, and 2 KB backup SRAM during main power loss-enables timekeeping and state retention. |
Key Features
| Feature | Design Value |
|---|---|
| LPBAM (Low-Power Background Autonomous Mode) | Enables DMA-driven peripheral chains (e.g., ADC→DMA→memory→filter) without CPU involvement-even in Stop 2 mode-reducing active time by >90% in sensor polling loops. |
| FlexPowerControl with SMPS+LDO | Integrated switch-mode power supply reduces active current by ~30% vs. LDO-only operation; on-the-fly switching avoids brownout during dynamic load changes. |
| CORDIC + FMAC co-processors | Accelerates trigonometric, hyperbolic, and filtering operations in <100 cycles-offloads 85% of motor control or FFT computation from CPU, preserving low-power budget. |
| Dual independent ADC subsystems | ADC1 (14-bit, 2.5 Msps) and ADC4 (12-bit, 2.5 Msps) operate concurrently with hardware oversampling and Stop 2 retention-enables synchronized multi-sensor acquisition with no wake-up latency. |
| Secure Root-of-Trust | Hardware-enforced boot entry, HDP (Hide Protection Area), and SFI ensure only cryptographically signed firmware executes-prevents unauthorized code injection and rollback attacks. |
Applications
| Smart Utility Meter | Wearable Health Monitor |
|---|---|
Use Scenario: Battery-operated gas/water meter with ultrasonic flow sensing, RF mesh backhaul, and 10-year lifespan. IC Role / Device Role / Timing Role: Main MCU executing metrology algorithms, managing secure OTA updates, and coordinating LPBAM-accelerated ADC sampling and CRC-verified packet transmission. Use Value: 90 nA Shutdown current extends battery life beyond 12 years; TrustZone isolates metrology firmware from communication stack; CAN FD enables field bus diagnostics. | Use Scenario: Clinical-grade ECG/PPG patch with motion artifact cancellation, Bluetooth LE telemetry, and onboard arrhythmia detection. IC Role / Device Role / Timing Role: Real-time sensor hub fusing analog front-end data via CORDIC/FMAC, running lightweight ML inference in SRAM, and enforcing secure firmware integrity before each boot. Use Value: Dual ADCs sample ECG and PPG simultaneously in Stop 2 mode; 370 nA Standby+RTC maintains time sync; TRNG seeds cryptographic keys for HIPAA-compliant BLE pairing. |
| Industrial Wireless Sensor Node | Secure Edge Gateway |
Use Scenario: IP67-rated vibration/temperature node in predictive maintenance system, powered by energy harvesting. IC Role / Device Role / Timing Role: Ultra-low-power host for MEMS accelerometer, temperature sensor, and LoRaWAN transceiver-orchestrating event-triggered wake-up and compressed data upload. Use Value: 1.4 μA Stop 3 mode preserves 16 KB context during intermittent harvesting; Octo-SPI interfaces with serial PSRAM for firmware staging; LPUART enables low-power debug over long distances. | Use Scenario: DIN-rail-mounted gateway aggregating Modbus RTU, CAN FD, and BLE devices in smart building HVAC control. IC Role / Device Role / Timing Role: Secure protocol translator with isolated secure world (TF-M) handling TLS 1.3 handshakes and non-secure world managing real-time I/O scheduling and watchdog supervision. Use Value: Dual-bank flash enables atomic firmware swaps; HASH accelerator speeds TLS record encryption; 82 I/Os support mixed industrial bus termination and level-shifting. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32U575RIT6Q | Higher flash (2 MB), larger SRAM (1 MB), dual-core Cortex-M33 option, enhanced crypto (AES-256, PKA), but larger UFBGA100 package and higher cost. | Targeted at complex edge AI inference and multi-protocol gateways requiring >512 KB code space and hardware PKA acceleration. | Select when needing >1 MB secure firmware storage, asymmetric crypto offload, or dual-core RTOS partitioning-not for cost-sensitive, size-constrained nodes. |
| RA4M3GDB00FJ#AC0 | Arm Cortex-M4F core, 1 MB flash, 256 KB SRAM, no TrustZone, Renesas Secure Crypto Engine (SCE9), 1.6 μA Stop mode, no LPBAM or CORDIC. | Designed for industrial HMI and motor control where deterministic FPU performance outweighs ultra-low-power autonomy and hardware root-of-trust. | Choose for legacy Renesas ecosystem integration or where SCE9 meets compliance needs-but not for sub-μA battery longevity or autonomous peripheral chaining. |
Compared with STM32U575RIT6Q, the STM32U535RCI6Q trades flash/SRAM capacity and advanced crypto for smaller LQFP64 footprint and lower system BOM cost; versus RA4M3GDB00FJ#AC0, it delivers superior ultra-low-power autonomy (90 nA vs. 1.6 μA), TrustZone-based isolation, and hardware math acceleration essential for secure, battery-constrained edge intelligence.
Availability
STM32U535RCI6Q is available at Aetrix Electronics and suitable for smart utility meters, wearable health monitors, industrial wireless sensor nodes, and secure edge gateways requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for STM32U535RCI6Q includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in microcontrollers, power management, sensors, and automotive ICs-with over 40 years of embedded systems innovation.
The STM32U5 series targets ultra-low-power, secure IoT endpoints and edge nodes, combining Arm TrustZone with ST's proprietary FlexPowerControl and LPBAM architecture to deliver best-in-class energy efficiency without compromising security or real-time capability.
FAQ
What is the maximum operating temperature range for STM32U535RCI6Q?
The STM32U535RCI6Q is qualified for industrial operation from –40 °C to +125 °C ambient temperature, with full specification compliance across this range-including all low-power modes, ADC accuracy, and flash endurance. This rating is verified per JEDEC JESD47 and ST's internal qualification standards.
Does STM32U535RCI6Q support hardware-accelerated TLS 1.3?
Yes-via integrated HASH accelerator (SHA-256/SHA-384), TRNG (NIST SP800-90B compliant), and TrustZone-protected key storage. When paired with TF-M and a certified TLS stack (e.g., Mbed TLS), it achieves full hardware-accelerated TLS 1.3 handshake and record encryption with minimal CPU overhead.
Can the STM32U535RCI6Q execute code directly from external Octo-SPI memory?
No-it does not support XIP (execute-in-place) from Octo-SPI. External memory accessed via OCTOSPI is limited to data transfers (e.g., firmware staging, sensor logs). Code execution remains restricted to internal flash or SRAM, ensuring deterministic timing and security boundary integrity.
How many wake-up pins are available in Shutdown mode?
The STM32U535RCI6Q provides 23 dedicated wake-up pins in Shutdown mode, all configurable as edge-triggered inputs. These pins retain their interrupt capability and can initiate full system wake-up from 90 nA quiescent current-critical for event-driven sensing in battery-critical applications.
STM32U535RCI6Q Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 64-UFBGA
- Series:
- STM32U5
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 160MHz
- Connectivity:
- CANbus, I2C, IrDA, LINbus, SAI, SmartCard, SPDIF, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
- Number of I/O:
- 47
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 274K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 15x12/14b SAR; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32U535RCI6Q FAQ
1.How can I place an order for STM32U535RCI6Q through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32U535RCI6Q on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32U535RCI6Q reliable?
The price and inventory of STM32U535RCI6Q are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32U535RCI6Q is usually 5 days.
3.What payment methods are accepted for STM32U535RCI6Q?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32U535RCI6Q transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32U535RCI6Q?
STM32U535RCI6Q orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32U535RCI6Q order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32U535RCI6Q?
For technical support, including STM32U535RCI6Q datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32U535RCI6Q requirements.
6.How does Aetrix verify that STM32U535RCI6Q is sourced from the original manufacturer or authorized distributors?
All STM32U535RCI6Q products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32U535RCI6Q meets industry standards.
7.What is the process for return or replacement of STM32U535RCI6Q?
All STM32U535RCI6Q units undergo pre-shipment inspection (PSI). If there is an issue with STM32U535RCI6Q, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32U535RCI6Q part is unused and in its original packaging.
Return procedure for STM32U535RCI6Q:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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