STMicroelectronics STM32U535VET6Q
- Part No.:
- STM32U535VET6Q
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
STM32U535VET6Q.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
STM32U535VET6Q from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 microcontroller with TrustZone® security, 240 DMIPS performance, 512 KB flash (ECC-enabled), 274 KB SRAM (up to 64 KB with ECC), and integrated SMPS for energy-efficient operation in battery-powered IoT edge nodes and secure sensor hubs.
For engineers reviewing the STM32U535VET6Q datasheet, STM32U535VET6Q pinout, STM32U535VET6Q application, or STM32U535VET6Q equivalent, key selection criteria include its 90 nA Shutdown mode, 14-bit 2.5-Msps ADC with Stop 2 autonomy, CAN FD interface, LPBAM peripheral autonomy, and dual-bank read-while-write flash for robust firmware updates.
Technical Context
The STM32U535VET6Q implements a dual-core security architecture: the Cortex-M33 core executes in both Secure and Non-secure states under Arm TrustZone®, while the GTZC (Global TrustZone Controller) enforces memory, peripheral, and I/O isolation. Its FlexPowerControl system integrates LDO and SMPS with on-the-fly voltage scaling and dynamic power state transitions.
It features ART Accelerator with 8-KB instruction cache and 4-KB data cache, enabling zero-wait-state execution at up to 160 MHz. The low-power design includes LPDMA, LPGPIO, and four independent low-power timers functional down to Stop 2 mode - all coordinated via hardware-triggered LPBAM sequences without CPU intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone®, FPU, MPU, and DSP extensions - enables secure real-time control with hardware-enforced privilege separation. |
| Max Clock / Performance | 160 MHz / 240 DMIPS - supports high-throughput signal processing and real-time protocol stacks (e.g., CAN FD, USB FS) without throttling. |
| Flash Memory | 512 KB with ECC, dual-bank RWW - allows safe over-the-air firmware updates with background verification and zero-downtime swapping. |
| SRAM | 274 KB total, including 64 KB with ECC - provides large, fault-tolerant working memory for cryptographic operations and sensor fusion buffers. |
| Low-Power Modes | 90 nA Shutdown, 370 nA Standby+RTC, 1.4 µA Stop 3 (16 KB SRAM retained) - extends battery life in multi-year deployments (e.g., smart meters, wearables). |
| Analog Peripherals | 14-bit 2.5-Msps ADC (autonomous in Stop 2), dual 12-bit DACs, OPAMP with PGA, ultra-low-power comparator - enables precision analog sensing without wake-up latency. |
| Security Features | TrustZone, 96-bit UID, 512-byte OTP, HASH accelerator, NIST SP800-90B TRNG, Secure Firmware Install (SFI) - meets PSA Level 3 and SESIP certification prerequisites. |
| Communication Interfaces | 1× CAN FD, 1× USB FS (host/device), 5× USART/LPUART, 4× I²C FM+, 3× SPI, 1× SAI, 1× SDMMC, OCTOSPI - supports mixed wired/wireless edge node connectivity with minimal external components. |
Pinout & Package
LQFP100 (14 × 14 mm, 0.5 mm pitch) package with 100 pins - suitable for industrial-grade PCB assembly and thermal management in space-constrained applications.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VDDIO2 | Core, analog, and I/O power supplies | Independent 1.71–3.6 V domains enable precise analog measurement and 5V-tolerant I/O interfacing simultaneously. |
| PA0–PA15, PB0–PB15, etc. (82 total) | General-purpose I/Os | Up to 82 fast GPIOs with interrupt capability; most are 5V-tolerant and support independent 1.08–3.6 V supply for mixed-voltage systems. |
| NRST | Active-low reset input | Asynchronous reset with internal pull-up; compatible with external reset supervisors and push-button recovery circuits. |
| BOOT0 | Boot mode selection | Configures boot source (system memory, embedded flash, or SRAM); sampled at power-on reset and hard reset only. |
| SWCLK, SWDIO | Serial Wire Debug interface | 2-pin debug port supporting full SWD functionality (programming, trace, real-time variable monitoring) without JTAG overhead. |
| VREF+ / VREF– | ADC reference inputs | Dedicated differential reference pins for high-accuracy 14-bit ADC conversions, decoupled from VDDA noise. |
Key Features
| Feature | Design Value |
|---|---|
| LPBAM (Low-Power Background Autonomous Mode) | Enables DMA-driven peripheral chains (e.g., ADC → DMA → AES → memory) without CPU wake-up - reduces active time by >90% in sensor polling cycles. |
| FlexPowerControl with SMPS | Integrated step-down SMPS replaces external DC/DC; achieves 2.2 µA Stop 3 (full SRAM) and 16.3 µA/MHz Run mode @ 3.3 V - cuts system power by 3× vs. LDO-only MCUs. |
| CORDIC + FMAC co-processors | Hardware acceleration for trigonometric (sin/cos/tan) and filter coefficient computation - offloads 85% of math-intensive tasks from Cortex-M33, preserving bandwidth for application logic. |
| Secure Root-of-Trust | Immutable boot entry, HDP (Hide Protection Area), and embedded RSS (Root-Secure Services) - ensures verified boot and prevents unauthorized firmware injection at factory or field. |
| VBAT domain retention | RTC + 32×32-bit backup registers + 2 KB backup SRAM powered from VBAT - maintains timekeeping and critical state across main power loss (e.g., smart lock battery swap). |
| OCTOSPI interface | Single 8-line interface supporting XIP (execute-in-place) from external Octal Flash - eliminates external RAM for code storage, reducing BOM count and PCB area. |
Applications
| Smart Utility Metering | Industrial Predictive Maintenance Sensor |
|---|---|
Use Scenario: Battery-powered gas/water meter with 10-year lifespan, periodic pressure/temperature readings, and encrypted LoRaWAN transmission. IC Role / Device Role / Timing Role: Primary MCU executing secure firmware, managing LPBAM-triggered ADC sampling, AES-128 encryption, and CAN FD diagnostics bus. Use Value: 90 nA Shutdown current and VBAT-secured RTC enable accurate timestamping and calendar-based wake-up - eliminating external real-time clock IC and saving 0.8 mm² PCB area. |
Use Scenario: Vibration/temperature/acoustic sensor node mounted on motor housing, transmitting FFT-processed data via BLE or NB-IoT. IC Role / Device Role / Timing Role: Real-time signal processor running CORDIC/FMAC-accelerated FFT, autonomous ADC oversampling, and secure OTA update handler. Use Value: 14-bit 2.5-Msps ADC with hardware oversampling delivers 16-bit effective resolution for vibration analysis - avoiding external sigma-delta ADC and associated anti-aliasing filters. |
| Secure Wearable Health Monitor | Automotive Body Control Module (BCM) Subsystem |
Use Scenario: ECG/PPG patch with medical-grade analog front-end, Bluetooth LE connectivity, and tamper-resistant firmware updates. IC Role / Device Role / Timing Role: Trusted execution environment host for biometric algorithm, secure key storage, and isolated ADC/DAC paths for analog signal conditioning. Use Value: TrustZone-enforced memory isolation prevents malicious apps from accessing raw ECG samples - satisfying IEC 62304 Class B software safety requirements. |
Use Scenario: Low-power door module controlling window lift, mirror fold, and interior lighting with CAN FD communication to central gateway. IC Role / Device Role / Timing Role: CAN FD node controller with hardware message filtering, LP timers for PWM dimming, and tamper detection via TSC capacitive sensing. Use Value: 4.6 µA Stop 2 mode with full SRAM retains window position and user preferences during vehicle sleep - eliminating need for external non-volatile memory. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32L562VEJ6 | Same Cortex-M33 core and TrustZone, but 256 KB flash, no SMPS, higher 1.1 µA Stop 2 current, no OCTOSPI or CAN FD. | Lacks CAN FD and external memory interface - unsuitable for automotive body networks or expandable sensor hubs requiring external flash. | Select when cost-sensitive designs prioritize basic security and analog features over connectivity and memory scalability. |
| NXP LPC55S69JBD100 | Dual Cortex-M33 cores, 640 KB flash, no SMPS, 2.1 µA Stop mode, lacks LPBAM, no dedicated OCTOSPI or CAN FD controller. | Higher active power and no autonomous peripheral chaining - limits battery life in duty-cycled sensor nodes below 1 µA average. | Prefer for compute-heavy applications (e.g., voice AI preprocessing) where dual-core parallelism outweighs ultra-low-power runtime needs. |
Compared with STM32L562VEJ6, the STM32U535VET6Q delivers 2× flash, integrated SMPS for 3× lower Stop-mode current, and CAN FD/OCTOSPI for scalable connectivity; versus LPC55S69JBD100, it offers superior LPBAM autonomy and 40% lower typical active power - making it optimal for long-life, secure, connected edge devices.
Availability
STM32U535VET6Q is available at Aetrix Electronics and suitable for smart utility metering, industrial predictive maintenance sensors, secure wearable health monitors, and automotive body control modules requiring stable component supply across multi-year production cycles.
Supply support for STM32U535VET6Q includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog products for industrial, automotive, and consumer markets.
The STM32U5 series is ST's flagship ultra-low-power secure MCU line, engineered specifically for battery-operated IoT endpoints requiring PSA Certified Level 3 security, sub-µA sleep currents, and hardware-accelerated cryptography - targeting certified edge intelligence deployment.
FAQ
What is the maximum operating temperature range for STM32U535VET6Q?
The STM32U535VET6Q is rated for –40 °C to +125 °C ambient operation, validated per JEDEC JESD22-A104. This extended range supports deployment in under-hood automotive subsystems, industrial motor drives, and outdoor utility infrastructure without derating or external thermal management.
Does STM32U535VET6Q support hardware-accelerated TLS stack execution?
Yes - the integrated HASH accelerator, NIST SP800-90B TRNG, and TrustZone-protected memory enable efficient TLS 1.2/1.3 handshakes. ST's mbed TLS port leverages these blocks to achieve <150 ms RSA-2048 signature generation and <80 ms AES-GCM encryption at 160 MHz - verified in AN5513 application note.
How many wake-up pins are available in Shutdown mode?
The STM32U535VET6Q provides 23 dedicated wake-up pins in Shutdown mode, each configurable as edge-triggered inputs with independent sensitivity control. These pins retain full interrupt capability while consuming only 90 nA total - enabling responsive event-driven wake-up from deepest power state.
Is the OCTOSPI interface capable of execute-in-place (XIP) operation?
Yes - the OCTOSPI interface supports true XIP from external Octal Flash devices (e.g., Micron MT35XUxx), allowing direct code execution without loading into internal flash or SRAM. This is enabled via the OCTOSPI memory-mapped region and requires no CPU intervention after initial configuration.
STM32U535VET6Q Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 100-LQFP
- Series:
- STM32U5
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 160MHz
- Connectivity:
- CANbus, I2C, IrDA, LINbus, SAI, SmartCard, SPDIF, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
- Number of I/O:
- 79
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 274K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 18x12/14b SAR; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32U535VET6Q FAQ
1.How can I place an order for STM32U535VET6Q through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32U535VET6Q on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32U535VET6Q reliable?
The price and inventory of STM32U535VET6Q are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32U535VET6Q is usually 5 days.
3.What payment methods are accepted for STM32U535VET6Q?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32U535VET6Q transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32U535VET6Q?
STM32U535VET6Q orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32U535VET6Q order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32U535VET6Q?
For technical support, including STM32U535VET6Q datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32U535VET6Q requirements.
6.How does Aetrix verify that STM32U535VET6Q is sourced from the original manufacturer or authorized distributors?
All STM32U535VET6Q products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32U535VET6Q meets industry standards.
7.What is the process for return or replacement of STM32U535VET6Q?
All STM32U535VET6Q units undergo pre-shipment inspection (PSI). If there is an issue with STM32U535VET6Q, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32U535VET6Q part is unused and in its original packaging.
Return procedure for STM32U535VET6Q:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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