STMicroelectronics STM32U545CEU6TR
- Part No.:
- STM32U545CEU6TR
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 48-UFQFN Exposed Pad
- Datasheet:
-
STM32U545CEU6TR.pdf
- Description:
- IC MCU 32BIT 512KB FLSH 48UFQFPN
- Quantity:
- Payment:

- Shipping:

Inventory:1,152
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Product details
Overview
STM32U545CEU6TR from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 microcontroller with TrustZone® security, 512 KB flash, 274 KB SRAM, and hardware crypto accelerators. It delivers 240 DMIPS at up to 160 MHz, supports LPBAM autonomous peripheral operation down to Stop 2 mode, and operates across –40 °C to +85 °C. It targets secure, battery-powered IoT edge nodes requiring real-time sensing, encrypted telemetry, and long-term energy autonomy.
For engineers reviewing the STM32U545CEU6TR datasheet, STM32U545CEU6TR pinout, STM32U545CEU6TR application, or STM32U545CEU6TR equivalent, key selection considerations include TrustZone-enforced memory isolation, 90 nA Shutdown mode with 23 wake-up pins, dual AES coprocessors (one DPA-resistant), Octo-SPI on-the-fly decryption, and ULPMark™-CP score of 464.
Technical Context
The device integrates an Arm Cortex-M33 core with MPU, FPU, and TrustZone®, enabling secure firmware partitioning between secure/non-secure worlds. Its ART Accelerator includes 8-Kbyte instruction cache and 4-Kbyte data cache for zero-wait-state execution from flash and external memories.
Power architecture combines embedded LDO and SMPS step-down converter with dynamic voltage scaling and switch-on-the-fly capability. Low-power modes are hierarchically structured: Shutdown (90 nA), Standby (200 nA), Stop 2 (3.0 µA with 16-Kbyte SRAM), and Run mode (16.3 μA/MHz @ 3.3 V).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone®, FPU, and DSP extensions - enables secure real-time control with cryptographic offload |
| Max Clock / Performance | 160 MHz / 240 DMIPS - supports high-throughput sensor fusion and protocol stacks without performance throttling |
| Flash Memory | 512 KB with ECC and read-while-write - ensures reliable firmware storage and over-the-air update resilience |
| SRAM | 274 KB total, including up to 64 KB with ECC enabled - provides robust data buffering for secure runtime contexts |
| Low-Power Modes | 90 nA Shutdown, 200 nA Standby, 3.0 µA Stop 2 (16-KB SRAM) - extends battery life in intermittent-sensing applications |
| Crypto Acceleration | Dual AES coprocessors (one DPA-resistant), PKA, HASH, RNG (NIST SP800-90B compliant) - enables TLS 1.3 handshake in <100 ms with minimal CPU load |
| ULPMark™ Score | 464 ULPMark™-CP - benchmark-validated efficiency for energy-constrained wireless sensor nodes |
| Security Certification | SESIP3 and PSA Level 3 Certified Assurance Target - meets industrial and medical IoT compliance requirements |
Pinout & Package
STM32U545CEU6TR is housed in a 48-pin UFQFPN package (7 × 7 mm, 0.5 mm pitch), optimized for space-constrained portable and wearable designs. The package supports reflow soldering and offers thermal performance suitable for continuous operation in ambient temperatures up to +85 °C.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VDDIO2 | Main, analog, and I/O power supplies | Independent 1.71–3.6 V domains enable mixed-signal integrity and flexible rail sequencing |
| VSS, VSSA | Digital and analog ground returns | Separate ground planes minimize noise coupling between digital logic and ADC/DAC paths |
| NRST | Active-low reset input | Asynchronous reset with internal pull-up; supports external debounced push-button or supervisor IC integration |
| BOOT0 | Boot mode selection | Configures boot source (system memory, flash, or SRAM); sampled at power-up only |
| PA0–PA15, PB0–PB15, PC0–PC15, PD0–PD15, PE0–PE15 | General-purpose I/Os | Up to 82 fast I/Os; most 5V-tolerant, 14 support independent 1.08–3.6 V supply for interfacing with low-voltage peripherals |
| PA13/PA14/PA15 | SWD debug interface | Serial Wire Debug (SWD) pins - enable programming and real-time trace without JTAG overhead |
| PF0–PF15 | Additional GPIO bank | Supports alternate functions including OCTOSPI, FDCAN, SAI, and USB FS; critical for multi-interface expansion |
| PC13/PC14/PC15 | RTC oscillator inputs | Connect 32.768 kHz crystal for hardware calendar and tamper detection with sub-second accuracy |
Key Features
| Feature | Design Value |
|---|---|
| LPBAM (Low-Power Background-Autonomous Mode) | Enables DMA-driven peripheral chains (e.g., ADC → DMA → Crypto → SRAM) while CPU remains in Stop 2 - eliminates wake-up latency for periodic sensing |
| TrustZone + GTZC | Global TrustZone Controller enforces hardware-isolated secure/non-secure memory and peripheral access - prevents unauthorized firmware modification or data exfiltration |
| On-the-fly Octo-SPI Decryption (OTFDEC) | Decrypts external flash contents transparently during fetch - allows secure code execution from external memory without exposing plaintext firmware |
| VBAT Domain | Supplies RTC, 32 × 32-bit backup registers, and 2-Kbyte backup SRAM - maintains timekeeping and state across main power loss |
| CORDIC + FMAC | Hardware-accelerated trigonometric and filter math - reduces CPU load by >70% in motor control or audio preprocessing tasks |
| Secure Firmware Installation (SFI) | Leverages embedded Root-Secure Services (RSS) to validate and install signed firmware images - establishes immutable root-of-trust at first boot |
Applications
| Smart Utility Meter | Wearable Health Monitor |
|---|---|
Use Scenario: Battery-powered gas/water meter collecting pressure, temperature, and flow data every 15 minutes, transmitting via NB-IoT. IC Role / Device Role / Timing Role: Main controller executing secure sensor acquisition, AES-GCM encryption, and LTE-M stack; RTC maintains precise timestamping for billing cycles. Use Value: 90 nA Shutdown current extends 10-year battery life; TrustZone isolates metering firmware from communication stack to prevent tampering. | Use Scenario: Clinical-grade wristband measuring ECG, SpO₂, and motion using capacitive touch and analog front-end. IC Role / Device Role / Timing Role: Real-time signal processor running CORDIC-based QRS detection and FMAC-based adaptive filtering; LPBAM automates ADC sampling and oversampling without CPU intervention. Use Value: 14-bit ADC (2.5 Msps) with hardware oversampling achieves >16 ENOB; 370 nA Standby with RTC preserves session state between measurements. |
| Industrial Wireless Sensor Node | Secure Edge Gateway |
Use Scenario: IP67-rated vibration and temperature node deployed in factory machinery, reporting via LoRaWAN. IC Role / Device Role / Timing Role: Autonomous edge node managing sensor fusion (accelerometer + thermistor), secure OTA updates, and tamper detection via TAMP peripheral. Use Value: Dual AES engines allow concurrent encryption of sensor data and signature verification of firmware patches; ULPMark™-CP 464 validates energy-per-inference efficiency. | Use Scenario: Field-deployable gateway aggregating Modbus RTU, CAN FD, and BLE devices before forwarding to cloud via TLS 1.3. IC Role / Device Role / Timing Role: Secure protocol translator with TrustZone-protected key storage, FDCAN controller, and USB full-speed host for peripheral bridging. Use Value: PSA Level 3 certification enables compliance with IEC 62443-3-3; 274 KB SRAM hosts multiple concurrent TLS sessions and packet buffering. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32U575ZIT6 | Higher pin count (144-LQFP), 2 MB flash, 1 MB SRAM, dual-core Cortex-M33 option, no OTFDEC | Targeted at complex HMI gateways requiring larger code footprint and display interfaces | Select when needing >512 KB flash or LCD-TFT controller; not drop-in due to package and peripheral differences |
| NXP LPC55S69JBD100 | Arm Cortex-M33, 640 KB flash, 320 KB SRAM, no TrustZone-certified bootloader, lower ULPMark™-CP (321) | Suitable for cost-sensitive consumer IoT where PSA Level 3 is not mandated | Choose for simpler BOMs and legacy toolchain compatibility; lacks SESIP3 certification and VBAT-RTC retention |
Compared with STM32U545CEU6TR, the STM32U575ZIT6 offers greater memory and interface scalability but sacrifices Octo-SPI on-the-fly decryption and compact 48-pin form factor; the LPC55S69JBD100 provides competitive compute but lacks PSA Level 3 assurance and fails to match 464 ULPMark™-CP efficiency in deep-sleep telemetry cycles.
Availability
STM32U545CEU6TR is available at Aetrix Electronics and suitable for smart utility meters, wearable health monitors, industrial wireless sensor nodes, and secure edge gateways requiring stable component supply across multi-year production lifecycles.
Supply support for STM32U545CEU6TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in microcontrollers, power management, sensors, and automotive ICs.
The STM32U5 series is designed for ultra-low-power, security-critical embedded applications - combining Arm TrustZone, PSA-certified firmware, and sub-µA sleep modes to serve battery-operated IoT endpoints and industrial edge devices.
FAQ
What is the maximum operating frequency and associated performance metric?
The STM32U545CEU6TR runs at up to 160 MHz with an ART Accelerator delivering 240 DMIPS (Dhrystone 2.1). Its 1.5 DMIPS/MHz efficiency and 651 CoreMark® score confirm deterministic real-time throughput suitable for sensor fusion and protocol stacks without throttling.
Does this MCU support external memory interfaces with hardware security?
Yes - it features one Octo-SPI interface with integrated On-the-Fly Decryption (OTFDEC), enabling secure execution from external flash. The OTFDEC engine uses AES-128 to decrypt instructions transparently during fetch, preventing firmware exposure while maintaining performance.
How many wake-up pins are available in Shutdown mode, and what is the typical current draw?
In Shutdown mode, 23 dedicated wake-up pins are active, with a typical current consumption of 90 nA at 3.3 V and 25 °C. This enables ultra-long battery life in applications requiring infrequent event-triggered wake-up, such as leak detection or door-open alerts.
Is the device qualified for extended temperature operation beyond commercial grade?
Yes - the STM32U545CEU6TR is rated for operation from –40 °C to +85 °C, meeting industrial temperature requirements. It does not support the +125 °C variant (e.g., STM32U545xxI), which is designated by suffix 'I' in the part number family.
STM32U545CEU6TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 48-UFQFN Exposed Pad
- Series:
- STM32U5
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 160MHz
- Connectivity:
- CANbus, I2C, IrDA, LINbus, MMC/SD/SDIO, SAI, SmartCard, SPDIF, SPI, UART/USART, USB, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, LCD, Motor Control PWM, POR, PWM, WDT
- Number of I/O:
- 37
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 274K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 11x12/14b SAR; D/A 2x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32U545CEU6TR FAQ
1.How can I place an order for STM32U545CEU6TR through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32U545CEU6TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32U545CEU6TR reliable?
The price and inventory of STM32U545CEU6TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32U545CEU6TR is usually 5 days.
3.What payment methods are accepted for STM32U545CEU6TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32U545CEU6TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32U545CEU6TR?
STM32U545CEU6TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32U545CEU6TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32U545CEU6TR?
For technical support, including STM32U545CEU6TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32U545CEU6TR requirements.
6.How does Aetrix verify that STM32U545CEU6TR is sourced from the original manufacturer or authorized distributors?
All STM32U545CEU6TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32U545CEU6TR meets industry standards.
7.What is the process for return or replacement of STM32U545CEU6TR?
All STM32U545CEU6TR units undergo pre-shipment inspection (PSI). If there is an issue with STM32U545CEU6TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32U545CEU6TR part is unused and in its original packaging.
Return procedure for STM32U545CEU6TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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