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STMicroelectronics STM32U545RET3
- Part No.:
- STM32U545RET3
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- -
- Datasheet:
-
STM32U545RET3.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 64LQFP
- Quantity:
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Inventory:3,677
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Product details
Overview
STM32U545RET3 from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 microcontroller with TrustZone® security, 512 KB flash, 274 KB SRAM, and hardware crypto accelerators (AES, PKA, HASH, RNG). It delivers 240 DMIPS at up to 160 MHz, supports LPBAM autonomous peripheral operation down to Stop 2 mode, and targets secure, battery-sensitive applications such as industrial wireless sensors and medical wearables.
For engineers reviewing the STM32U545RET3 datasheet, STM32U545RET3 pinout, STM32U545RET3 application, or STM32U545RET3 equivalent, key selection criteria include its 90 nA Shutdown current, SESIP3/PSA Level 3 certification, dual 14-/12-bit ADCs with Stop 2 autonomy, Octo-SPI on-the-fly decryption, and LQFP64 (10 × 10 mm) package compatibility with legacy STM32U5 footprint layouts.
Technical Context
The STM32U545RET3 integrates a dual-cache Arm Cortex-M33 core (8 KB I-Cache, 4 KB D-Cache), TrustZone-enabled memory isolation, and FlexPowerControl architecture enabling sub-µA low-power modes including 370 nA Standby with RTC and 1.4 µA Stop 3 with 16 KB SRAM retention. Its power system combines embedded LDO and SMPS with dynamic voltage scaling.
Security is implemented via hardware root of trust, secure boot with HDP protection, Secure Firmware Installation (SFI), and tamper-aware RTC/backup domain. Peripheral-level TrustZone classification secures I/Os, memories, and interfaces-including FDCAN, USB FS, SAI, and Octo-SPI-while cryptographic acceleration includes DPA-resistant AES coprocessors and public-key accelerator.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone®, FPU, MPU, and DSP extensions - enables secure real-time control with deterministic floating-point math and memory partitioning. |
| Max Clock / Performance | 160 MHz / 240 DMIPS - achieves zero-wait-state execution from flash via ART Accelerator, supporting high-throughput sensor fusion or audio preprocessing. |
| Memory | 512 KB flash (ECC, RWW), 274 KB SRAM (up to 64 KB with ECC) - ensures data integrity in safety-critical firmware and runtime variables. |
| Low-Power Modes | 90 nA Shutdown, 370 nA Standby w/RTC, 1.4 µA Stop 3 w/16 KB SRAM - extends battery life in multi-year IoT deployments without external PMIC. |
| Crypto Acceleration | 2× AES (1 DPA-resistant), PKA, HASH, TRNG (NIST SP800-90B), OTFDEC - enables TLS 1.3 handshake in <100 ms and secure OTA updates without CPU load. |
| Analog Peripherals | 14-bit 2.5-Msps ADC (hardware oversampling), 12-bit ADC autonomous in Stop 2, 2× DAC, OPAMP+PGA, COMP - supports precision analog sensing with minimal wake-up latency. |
| Communication | 1× FDCAN, 1× USB FS (host/device), 4× I²C FM+, 5× USART/LPUART, 3× SPI, 1× SAI, 1× SDMMC - fits industrial fieldbus gateways and voice-enabled edge nodes. |
Pinout & Package
LQFP64 (10 × 10 mm, 0.5 mm pitch) package with exposed thermal pad; RoHS-compliant ECOPACK2 finish. Pin count: 64 leads, including 51 general-purpose I/Os (most 5V-tolerant), 14 I/Os with independent VDDIO supply (down to 1.08 V), and dedicated debug (SWD), reset, and power management pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VSS | Core power supply / ground | 1.71–3.6 V input; decoupling required per datasheet layout guidelines to maintain 160 MHz stability and low-noise analog performance. |
| VREF+, VREF– | Analog reference inputs | Enable precise ADC/DAC calibration; support external reference or internal 2.5 V buffered reference (VREFBUF). |
| PA0–PA15, PB0–PB15, etc. | General-purpose I/Os | Up to 51 GPIOs with interrupt capability; most tolerate 5 V, enabling direct interfacing with legacy logic or sensors without level shifters. |
| BOOT0 | Boot mode selection | Pulled low for main flash boot; used with NRST to enter system memory bootloader for field firmware recovery. |
| NRST | Active-low reset input | Asynchronous reset with internal pull-up; supports external reset supervisor ICs and manual reset button integration. |
| SWCLK, SWDIO | Serial Wire Debug interface | 2-pin debug port supporting full SWD protocol - enables non-intrusive trace, flash programming, and real-time variable monitoring. |
Key Features
| Feature | Design Value |
|---|---|
| LPBAM (Low-Power Background Autonomous Mode) | Enables DMA-driven peripheral chains (e.g., ADC → memory → timer → GPIO) without CPU wake-up - reduces active time by >90% in sensor logging. |
| TrustZone + GTZC | Hardware-enforced separation of secure/non-secure code and data; Global TrustZone Controller (GTZC) configures memory regions and peripheral access rights at boot. |
| Octo-SPI OTFDEC | On-the-fly decryption of external XIP flash using AES-128/256 - allows secure code execution from external memory without exposing plaintext firmware. |
| CORDIC + FMAC | Hardware trigonometric (sin/cos/tan) and filter coefficient computation - accelerates motor control algorithms and digital signal processing with <1 µs latency. |
| VBAT Domain | RTC + 32×32-bit backup registers + 2 KB backup SRAM powered independently - maintains timekeeping and critical state during main power loss. |
Applications
| Industrial Wireless Sensor Node | Secure Medical Wearable |
|---|---|
|
Use Scenario: Battery-powered vibration/temperature node transmitting encrypted telemetry via LoRaWAN every 15 minutes. IC Role / Device Role / Timing Role: Main controller executing LPBAM-triggered ADC sampling, crypto signing, and radio stack scheduling; RTC provides precise wakeup timing. Use Value: 90 nA Shutdown current enables 10+ year battery life; TrustZone isolates BLE stack from sensor firmware; OTFDEC secures firmware updates from cloud. |
Use Scenario: ECG patch with real-time arrhythmia detection, local data encryption, and Bluetooth LE transmission. IC Role / Device Role / Timing Role: Signal acquisition hub managing 14-bit ADC oversampling, CORDIC-based QRS detection, and secure TLS handshake before upload. Use Value: 1.4 µA Stop 3 mode preserves RAM context between heartbeats; dual ADCs enable simultaneous lead I/II acquisition; PSA Level 3 cert satisfies FDA cybersecurity guidance. |
| Smart Utility Meter | Asset Tracking Module |
|
Use Scenario: Gas/water meter with ultrasonic flow sensing, tamper detection, and NB-IoT reporting. IC Role / Device Role / Timing Role: Tamper-aware system controller handling TAMP inputs, RTC calendar, secure metering log storage, and FDCAN communication to metrology ASIC. Use Value: Active tampers detect enclosure breach and erase keys; VBAT domain retains metering history during power outage; SESIP3 cert meets EU Measuring Instruments Directive (MID). |
Use Scenario: GPS tracker in logistics container with motion-triggered location reporting and geofence alerts. IC Role / Device Role / Timing Role: Power-optimized host managing LPTIM-based motion wake-up, GPS UART parsing, AES-encrypted payload generation, and LTE-M modem control. Use Value: 370 nA Standby with RTC enables months of shelf life; 512-byte OTP stores device identity; 1.08 V I/O support interfaces directly with low-voltage GNSS modules. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32U575RIT6 | Same U5 series, but 2 MB flash, 1 MB SRAM, dual-core (Cortex-M33 + Cortex-M0+), additional crypto engines (SAES, PKA v2), and higher temp grade (–40 °C to +125 °C). | Targeted at complex edge AI inference or dual-domain secure boot where larger code space and auxiliary core offload are required. | Select when >1 MB flash or asymmetric core partitioning (e.g., secure monitor + application core) is needed; not drop-in due to pinout and power sequencing differences. |
| RA4M3GDB001#AC0 | Renesas RA4M3 with Cortex-M33, 1 MB flash, 256 KB SRAM, TrustZone, but no OTFDEC, lower ULPMark-CP (342 vs 464), and no LPBAM. | Suitable for cost-sensitive industrial HMI or gateway applications where external flash encryption is handled in software and autonomous peripheral chaining is unnecessary. | Choose for simpler toolchain integration (Flexible Software Package) and lower unit cost; verify absence of OTFDEC and LPBAM does not impact security or power budget. |
Compared with STM32U545RET3, the STM32U575RIT6 offers greater memory and dual-core flexibility at higher cost and complexity, while the RA4M3GDB001 trades advanced low-power autonomy and hardware crypto depth for broader middleware support and lower BOM cost - making the U545RET3 optimal for constrained, long-life, high-security edge nodes.
Availability
STM32U545RET3 is available at Aetrix Electronics and suitable for industrial wireless sensor nodes, secure medical wearables, smart utility meters, and asset tracking modules requiring stable component supply across multi-year production cycles.
Supply support for STM32U545RET3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, MEMS, and automotive semiconductors since 1987.
The STM32U5 series is ST's flagship ultra-low-power MCU platform built on the Arm Cortex-M33 core, targeting secure, battery-operated edge devices in industrial, healthcare, and smart infrastructure applications - emphasizing energy efficiency, hardware-rooted security, and peripheral autonomy.
FAQ
What is the maximum operating temperature range for the STM32U545RET3?
The STM32U545RET3 is qualified for operation from –40 °C to +85 °C (industrial grade); certain variants (e.g., STM32U545xxV) extend to +125 °C, but the RET3 suffix specifically denotes the 85 °C grade. This range is validated per JEDEC JESD47 and includes full functionality of all peripherals, crypto accelerators, and LPBAM features under thermal stress.
Does the STM32U545RET3 support external memory interfaces beyond Octo-SPI?
No - the STM32U545RET3 provides only one Octo-SPI interface (OCTOSPI1) for external memory expansion. It does not include FSMC, Quad-SPI, or parallel NOR/NAND controllers. External code/data must be accessed via OCTOSPI with optional on-the-fly decryption (OTFDEC), and XIP execution is supported with proper cache configuration and latency tuning.
How many independent power domains does the STM32U545RET3 have?
The STM32U545RET3 implements three primary power domains: VDD/VSS (core/digital), VDDA/VSSA (analog), and VBAT (backup/RTC). Each has dedicated regulators and supervision - VDD supports SMPS/LDO switching, VDDA requires clean 2.4–3.6 V for ADC/DAC accuracy, and VBAT sustains RTC and backup registers during main power loss.
Can the STM32U545RET3 achieve PSA Certified Level 3 without external components?
Yes - the STM32U545RET3 is certified to PSA Certified Level 3 and SESIP3 Assurance Target as a standalone device. Certification covers on-chip TrustZone, secure boot, cryptographic accelerators, tamper detection, and secure debug disable - no external secure element or discrete crypto IC is required to meet this assurance level.
STM32U545RET3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- -
- Series:
- -
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
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- Core Size:
- -
- Speed:
- -
- Connectivity:
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- Peripherals:
- -
- Number of I/O:
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- Program Memory Size:
- -
- Program Memory Type:
- -
- EEPROM Size:
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- RAM Size:
- -
- Voltage - Supply (Vcc/Vdd):
- -
- Data Converters:
- -
- Oscillator Type:
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- Operating Temperature:
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- Supplier Device Package:
STM32U545RET3 FAQ
1.How can I place an order for STM32U545RET3 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32U545RET3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32U545RET3 reliable?
The price and inventory of STM32U545RET3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32U545RET3 is usually 5 days.
3.What payment methods are accepted for STM32U545RET3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32U545RET3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32U545RET3?
STM32U545RET3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32U545RET3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32U545RET3?
For technical support, including STM32U545RET3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32U545RET3 requirements.
6.How does Aetrix verify that STM32U545RET3 is sourced from the original manufacturer or authorized distributors?
All STM32U545RET3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32U545RET3 meets industry standards.
7.What is the process for return or replacement of STM32U545RET3?
All STM32U545RET3 units undergo pre-shipment inspection (PSI). If there is an issue with STM32U545RET3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32U545RET3 part is unused and in its original packaging.
Return procedure for STM32U545RET3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32U545RET3 Tags
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