My Inquiry
My Account
STMicroelectronics STM32U545VET6
- Part No.:
- STM32U545VET6
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
STM32U545VET6.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 100LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:2,322
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32U545VET6 from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 microcontroller with TrustZone® security, 512 KB flash, 274 KB SRAM, and hardware crypto accelerators (AES, PKA, HASH, RNG). It delivers 240 DMIPS at up to 160 MHz, supports LPBAM autonomous peripheral operation down to Stop 2 mode, and targets secure, battery-sensitive applications such as industrial wireless sensors and medical wearables.
For engineers reviewing the STM32U545VET6 datasheet, STM32U545VET6 pinout, STM32U545VET6 application, or STM32U545VET6 equivalent, key selection criteria include its 90 nA Shutdown current, SESIP3/PSA Level 3 certification, dual 14-/12-bit ADCs with Stop 2 autonomy, Octo-SPI on-the-fly decryption, and LQFP100 package compatibility with legacy STM32U5 designs.
Technical Context
The STM32U545VET6 integrates an Arm Cortex-M33 core with TrustZone-enabled memory and peripheral isolation, MPU, FPU, and DSP extensions. Its ART Accelerator includes 8-KB instruction cache and 4-KB data cache for zero-wait-state execution from flash and external memories.
Power architecture combines embedded LDO and SMPS step-down converter with dynamic voltage scaling and switch-on-the-fly capability. Security relies on root-of-trust boot entry, secure hide protection area (HDP), and hardware-unique key (HUK) for secure firmware installation and upgrade via TF-M.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone®, FPU, MPU, and DSP extensions - enables secure real-time control with deterministic floating-point math and memory partitioning. |
| Max Clock Speed | 160 MHz - supports 240 DMIPS performance while maintaining sub-μA/MHz efficiency in Run mode (16.3 μA/MHz @ 3.3 V). |
| Flash / SRAM | 512 KB flash with ECC and 2-bank RWW; 274 KB SRAM (up to 64 KB with ECC ON) - enables robust firmware updates and large buffer storage for sensor fusion or audio processing. |
| Low-Power Modes | 90 nA Shutdown, 370 nA Standby with RTC, 1.4 μA Stop 3 with 16 KB SRAM - extends battery life in multi-year IoT endpoints without compromising wake-up responsiveness. |
| Crypto Acceleration | Dual AES coprocessors (one DPA-resistant), PKA, HASH, NIST SP800-90B TRNG - offloads TLS 1.2/1.3 handshake and secure boot verification in under 10 ms. |
| Analog Peripherals | 14-bit 2.5-Msps ADC (autonomous in Stop 2), 12-bit DAC, OPAMP with PGA, ultra-low-power comparator - supports high-fidelity sensor signal conditioning with minimal active power. |
| Communication | 1 CAN FD, 4 I²C FM+, 5 USART/LPUART, 1 USB FS host/device, Octo-SPI with OTFDEC - enables mixed wired/wireless connectivity including automotive-grade diagnostics and encrypted external flash expansion. |
Pinout & Package
LQFP100 (14 × 14 mm, 0.5 mm pitch) package with exposed thermal pad; 100-pin layout supporting full peripheral mapping including dual ADC inputs, Octo-SPI bus, CAN FD transceiver pins, and dedicated TrustZone-secured GPIO banks.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VSS | Core power supply and ground | Supports 1.71–3.6 V operation; decoupling required per datasheet Section 5.3.6 for stable SMPS/LDO coexistence. |
| VBAT | Backup domain supply | Powers RTC, 32×32-bit backup registers, and 2 KB backup SRAM during main power loss - enables calendar retention for >10 years on coin cell. |
| NRST | Active-low reset input | Asynchronous reset with internal pull-up; compatible with open-drain external supervisors per Section 5.3.16. |
| PA13/PA14 | SWDIO/SWCLK debug interface | Serial-wire debug pins with built-in pull-ups; functional in all low-power modes except Shutdown - enables field firmware update without waking CPU core. |
| PC10/PC11 | CAN FD TX/RX | Dedicated differential signaling pins with internal termination support - meets ISO 11898-1:2015 timing and noise immunity requirements for automotive body networks. |
| PF0–PF13 | Octo-SPI I/O (IO0–IO7, SCK, DQS, CS) | Configurable 8-line x1/x2/x4/x8 interface for high-speed external flash; supports on-the-fly decryption (OTFDEC) with AES-128/256 keys stored in HUK-protected OTP. |
Key Features
| Feature | Design Value |
|---|---|
| LPBAM (Low-Power Background-Autonomous Mode) | Enables DMA-driven peripheral chains (e.g., ADC → DMA → AES → SRAM) without CPU intervention - reduces active time by >90% in sensor logging cycles. |
| TrustZone + GTZC | Global TrustZone Controller enforces secure/non-secure memory and peripheral access at hardware level - prevents unauthorized access to cryptographic keys or OTA update payloads. |
| ART Accelerator Caches | 8-KB instruction cache + 4-KB data cache eliminate wait states for flash and external memory accesses - sustains 160 MHz throughput with <1% CPU stall penalty. |
| Secure Firmware Installation (SFI) | Embedded Root-Secure Services (RSS) validate and install signed firmware images using HUK-derived keys - eliminates need for external secure element in Class B medical devices. |
| ULPMark™-CP Score | 464 - industry-leading energy efficiency benchmark for Cortex-M33 cores, confirming sub-μA active power in real-world sensor node workloads. |
Applications
| Industrial Wireless Sensor Node | Portable Medical Monitor |
|---|---|
Use Scenario: Battery-powered vibration/temperature node transmitting encrypted telemetry via LoRaWAN every 5 minutes. IC Role / Device Role / Timing Role: Main controller executing sensor fusion, AES-GCM encryption, and low-power radio scheduling; RTC triggers periodic wake-up with ±1 ppm accuracy. Use Value: 90 nA Shutdown current extends CR2032 battery life to >7 years; LPBAM allows ADC+crypto chain to complete in Stop 2 mode with only 3.0 µA draw. | Use Scenario: Wearable ECG patch with real-time arrhythmia detection and Bluetooth LE upload. IC Role / Device Role / Timing Role: Signal acquisition hub managing 14-bit ADC sampling at 2.5 Msps, CORDIC-based QRS detection, and secure BLE pairing via PSA-certified TF-M stack. Use Value: Dual ADC autonomy in Stop 2 mode enables continuous analog monitoring at <2 µA; TrustZone isolates patient health data from BLE stack. |
| Smart Building HVAC Controller | Automotive Body Control Module (BCM) |
Use Scenario: DIN-rail mounted controller regulating fan speed, valve position, and air quality via CO₂/VOC sensors. IC Role / Device Role / Timing Role: Real-time motor control hub with advanced timers (TIM1/TIM8), CAN FD diagnostics, and isolated I/O for 24 V actuator interfaces. Use Value: 240 DMIPS headroom supports PID + fuzzy logic control loops; 125 °C extended temperature rating ensures reliability in enclosed enclosures. | Use Scenario: Door module managing window lift, mirror fold, and interior lighting with LIN/UART diagnostics. IC Role / Device Role / Timing Role: Secure gateway bridging LIN slave nodes to CAN FD backbone; OTP stores vehicle-specific calibration and VIN-locked features. Use Value: SESIP3 certification satisfies UNECE R155 cybersecurity management system (CSMS) requirements; 512-byte OTP enables feature activation without cloud dependency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32U575VIT6 | Same package and pinout; adds 2 MB Octo-SPI memory interface and enhanced graphics (LTDC), but no DCMI or PSSI. | Better suited for HMI-rich applications (e.g., smart thermostat display); lacks camera interface needed for vision-based sensing. | Select when display output or larger external memory bandwidth is required over camera or parallel interface support. |
| RA4M3GDBM20#AC0 | Arm Cortex-M33, 1 MB flash, 384 KB SRAM, but no TrustZone hardware isolation or SESIP3 certification; uses Renesas Secure Crypto Engine instead of PSA Level 3. | Targeted at cost-sensitive industrial controls where formal security certification is not mandated by end-customer. | Choose for non-regulated environments where lower BOM cost outweighs need for PSA-certified secure boot and runtime attestation. |
Compared with STM32U545VET6, the STM32U575VIT6 offers higher memory bandwidth at the expense of camera interface support, while the RA4M3GDBM20#AC0 provides competitive performance without hardware-enforced TrustZone isolation or ULPMark™-validated ultra-low-power operation.
Availability
STM32U545VET6 is available at Aetrix Electronics and suitable for industrial wireless sensor nodes, portable medical monitors, smart building HVAC controllers, and automotive body control modules requiring stable component supply across multi-year production cycles.
Supply support for STM32U545VET6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and analog components for industrial, automotive, and consumer markets.
The STM32U5 series is ST's flagship ultra-low-power MCU line targeting PSA-certified secure edge devices, with the U545 variant optimized for balanced performance, memory, and peripheral integration in space-constrained LQFP100 designs.
FAQ
What is the maximum operating temperature range for STM32U545VET6?
The STM32U545VET6 is rated for –40 °C to +125 °C operation, validated per Section 5.3.1 of DS14216 Rev 5. This extended range supports deployment in engine bay proximity, industrial enclosures, and outdoor infrastructure where ambient temperatures exceed standard commercial limits.
Does STM32U545VET6 support hardware-based secure boot?
Yes - it implements a hardware-rooted secure boot sequence using unique boot entry, secure hide protection area (HDP), and embedded root-secure services (RSS). Boot image validation leverages the hardware-unique key (HUK) and PSA Level 3 certified TrustZone environment per Section 3.6 and Section 8 of the datasheet.
Can the Octo-SPI interface operate with on-the-fly decryption enabled?
Yes - the integrated OTFDEC engine decrypts Octo-SPI external memory reads in real time using AES-128/256 keys derived from the HUK. Decryption occurs transparently to software and is active in all run and stop modes, as specified in Section 3.37 and Table 132 of DS14216 Rev 5.
How many wake-up pins are available in Shutdown mode?
The STM32U545VET6 provides 23 dedicated wake-up pins in Shutdown mode, each capable of generating an interrupt to exit 90 nA deep-sleep state. Pin configuration and filtering are managed via the EXTI and PWR peripherals per Sections 3.19.2 and 3.9.3 of the reference manual.
STM32U545VET6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 100-LQFP
- Series:
- STM32U5
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 160MHz
- Connectivity:
- CANbus, I2C, IrDA, LINbus, MMC/SD/SDIO, SAI, SmartCard, SPDIF, SPI, UART/USART, USB, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, LCD, Motor Control PWM, POR, PWM, WDT
- Number of I/O:
- 82
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 274K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 20x12/14b SAR; D/A 2x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32U545VET6 FAQ
1.How can I place an order for STM32U545VET6 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32U545VET6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32U545VET6 reliable?
The price and inventory of STM32U545VET6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32U545VET6 is usually 5 days.
3.What payment methods are accepted for STM32U545VET6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32U545VET6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32U545VET6?
STM32U545VET6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32U545VET6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32U545VET6?
For technical support, including STM32U545VET6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32U545VET6 requirements.
6.How does Aetrix verify that STM32U545VET6 is sourced from the original manufacturer or authorized distributors?
All STM32U545VET6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32U545VET6 meets industry standards.
7.What is the process for return or replacement of STM32U545VET6?
All STM32U545VET6 units undergo pre-shipment inspection (PSI). If there is an issue with STM32U545VET6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32U545VET6 part is unused and in its original packaging.
Return procedure for STM32U545VET6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32U545VET6 Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
