STMicroelectronics STM32U575CGU3Q
- Part No.:
- STM32U575CGU3Q
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 48-UFQFN Exposed Pad
- Datasheet:
-
STM32U575CGU3Q.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 48UFQFPN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
STM32U575CGU3Q from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit MCU with TrustZone® and FPU, delivering 240 DMIPS at up to 160 MHz. It integrates 2 MB Flash (ECC-enabled, dual-bank read-while-write), 786 KB SRAM (with configurable ECC), and operates from 1.71 V to 3.6 V across –40 °C to +125 °C. Its LPBAM autonomous peripheral mode enables sensor data acquisition in Stop 2, making it ideal for battery-powered industrial IoT edge nodes with secure firmware updates.
For engineers reviewing the STM32U575CGU3Q datasheet, STM32U575CGU3Q pinout, STM32U575CGU3Q application, or STM32U575CGU3Q equivalent, key selection criteria include TrustZone-enforced secure boot, sub-µA low-power modes (e.g., 160 nA Shutdown), integrated SMPS support, 14-bit ADC with 2.5-Msps sampling, and UCPD-based USB Type-C® power delivery control.
Technical Context
The STM32U575CGU3Q implements a dual-core security architecture: the Cortex-M33 core executes in both Secure and Non-secure states under Arm TrustZone®, with dedicated GTZC peripherals enforcing memory and I/O isolation. Its FlexPowerControl system combines LDO and SMPS regulators, enabling dynamic voltage scaling and on-the-fly switching between power domains.
Real-time autonomy is enabled by LPBAM-low-power background autonomous mode-where peripherals (ADC, timers, DMA) operate without CPU intervention down to Stop 2 mode. The device supports secure firmware installation (SFI) via embedded root secure services (RSS) and TF-M–based over-the-air upgrades, with hardware accelerators including CORDIC, FMAC, HASH, and True RNG compliant with NIST SP800-90B.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | Arm Cortex-M33 with TrustZone®, FPU, MPU, 240 DMIPS @ 160 MHz |
| Flash Memory | 2 MB with ECC, dual-bank RWW, 100 kcycle endurance for 512 KB section |
| SRAM | 786 KB total: 722 KB with optional ECC (up to 322 KB protected), 16 KB retained in Stop 3 |
| Low-Power Modes | 160 nA Shutdown (24 wake-up pins), 530 nA Standby+RTC, 4.3 µA Stop 3 with full SRAM retention |
| Analog Peripherals | 14-bit ADC @ 2.5 Msps with hardware oversampling; two 12-bit DACs; two op-amps with PGA; two ultra-low-power comparators |
| Security Features | TrustZone®-secured I/O/memories/peripherals; 96-bit unique ID; 512-byte OTP; active tamper detection; secure hide protection area (HDP) |
| Communication | 1× CAN FD, 1× USB OTG FS, 1× UCPD (USB Type-C®/PD controller), 6× USART, 4× I²C, 3× SPI, 2× SAI, 2× SDMMC |
Pinout & Package
STM32U575CGU3Q is housed in a 48-pin UFQFPN package (7 × 7 mm, 0.5 mm pitch), optimized for space-constrained industrial and portable applications. This RoHS-compliant ECOPACK2 package supports reflow soldering and provides thermal performance suitable for extended temperature operation up to +125 °C.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD | Main power supply (1.71–3.6 V) | Supplies core, analog, and I/O domains; connects to internal LDO/SMPS output |
| VSS | Ground reference | Digital ground plane; must be low-impedance and separated from analog ground where possible |
| VBAT | Backup power supply | Retains RTC, 32×32-bit backup registers, and 2 KB backup SRAM during main power loss |
| NRST | Active-low reset input | Asynchronous external reset; triggers system reset and clears debug interface state |
| PA0–PA15 | General-purpose I/O bank A | Up to 136 fast I/Os total; most are 5V-tolerant; up to 14 support independent VDDIO down to 1.08 V |
| PC13–PC15 | Low-power oscillator inputs | LSE crystal connections (32.768 kHz) for RTC calibration and low-power clock source |
| PF0–PF1 | System control signals | BOOT0 (mode select) and BOOT1 (optional); determine boot source (system memory, Flash, or SRAM) |
| PA11/PA12 | USB OTG FS D+/D− | Full-speed USB 2.0 transceiver interface; requires external 1.5 kΩ pull-up on PA12 for enumeration |
Key Features
| Feature | Design Value |
|---|---|
| LPBAM (Low-Power Background Autonomous Mode) | Enables ADC, timers, and DMA to run unattended in Stop 2 mode-eliminating CPU wake-ups for periodic sensing |
| FlexPowerControl with SMPS | Integrated step-down converter reduces active-mode power by ~30% vs. LDO-only; supports dynamic voltage scaling during runtime |
| Secure Root of Trust | Hardware-enforced secure boot chain with unique boot entry, HDP, and RDP-level protection prevents unauthorized firmware execution |
| ART Accelerator with ICACHE/DCACHE | 8 KB instruction cache + 4 KB data cache enable zero-wait-state execution from Flash and external memories at 160 MHz |
| UCPD Peripheral | Dedicated USB Type-C®/Power Delivery controller handles CC logic, VCONN switching, and PD messaging without CPU overhead |
Applications
| Smart Utility Meter | Wireless Sensor Node |
|---|---|
Use Scenario: Battery-operated gas/water meter collecting pressure, temperature, and flow data hourly with encrypted transmission. IC Role / Device Role / Timing Role: Main application MCU executing metering algorithms, managing secure OTA updates, and controlling RF transceiver timing via LP timers. Use Value: 160 nA Shutdown current extends 10-year battery life; LPBAM allows ADC-triggered wake-up only when threshold exceeded-reducing average current to <1 µA. |
Use Scenario: Self-powered environmental node measuring air quality (PM2.5, CO₂), humidity, and ambient light in remote infrastructure. IC Role / Device Role / Timing Role: Central sensor hub with autonomous ADC sampling, cryptographic signing (HASH + RNG), and scheduled BLE/LoRaWAN transmission windows. Use Value: 530 nA Standby+RTC enables precise time-synchronized wake-ups; TrustZone isolates sensor data collection from network stack-preventing side-channel leakage. |
| Industrial PLC Edge Controller | Medical Wearable Monitor |
Use Scenario: DIN-rail mounted edge gateway aggregating Modbus RTU data from field devices and forwarding to cloud via Ethernet/Wi-Fi. IC Role / Device Role / Timing Role: Real-time deterministic controller running FreeRTOS with dual-bank Flash enabling safe firmware rollback after update failure. Use Value: Dual-bank Flash with RWW allows background firmware validation while maintaining live I/O control; 125 °C rating ensures reliability in enclosed cabinets. |
Use Scenario: Patch-style ECG/PPG monitor worn continuously for arrhythmia detection and sleep apnea screening. IC Role / Device Role / Timing Role: Ultra-low-power signal processor acquiring analog biosignals, performing real-time filtering (FMAC), and storing compressed waveform in backup SRAM. Use Value: 4.3 µA Stop 3 mode with full SRAM retention preserves context across sleep cycles; 14-bit ADC with hardware oversampling achieves >100 dB SNR for microvolt-level ECG resolution. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32L562VEJ6 | Same Cortex-M33 + TrustZone, but 512 KB Flash, 256 KB SRAM; no SMPS; max 110 MHz; lacks UCPD and Octo-SPI | Targeted at cost-sensitive, lower-compute secure applications (e.g., access control tokens) without USB-C or high-bandwidth memory needs | Select when full 2 MB Flash, SMPS efficiency, or USB Type-C PD control are not required-reduces BOM cost and layout complexity |
| RA4M3GDB0 | Renesas RA4M3: Cortex-M33 + TrustZone, 1 MB Flash, 384 KB SRAM, 120 MHz; includes SCE7 crypto accelerator but no SMPS or LPBAM | Focused on general-purpose secure HMI and gateway applications; stronger software ecosystem alignment with Renesas FSP | Prefer when leveraging Renesas' GUI frameworks or needing SCE7-accelerated AES-GCM/TLS offload-though lacks STM32U5's sub-µA stop modes |
Compared with STM32L562VEJ6, the STM32U575CGU3Q delivers 4× more Flash, integrated SMPS, and UCPD for USB-C systems; versus RA4M3GDB0, it offers superior ultra-low-power autonomy (LPBAM) and higher compute density (240 DMIPS), critical for battery-constrained edge AI inference.
Availability
STM32U575CGU3Q is available at Aetrix Electronics and suitable for industrial IoT gateways, medical wearables, smart utility meters, and battery-powered asset trackers requiring stable component supply across extended temperature and long product lifecycles.
Supply support for STM32U575CGU3Q includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog components for industrial, automotive, and consumer markets.
The STM32U5 series is ST's flagship ultra-low-power secure MCU line, engineered for energy-harvesting and battery-critical applications demanding Arm TrustZone security, sub-µA power states, and hardware-accelerated cryptography without compromising real-time responsiveness.
FAQ
What is the maximum operating frequency and corresponding DMIPS rating?
The STM32U575CGU3Q runs at up to 160 MHz with the ART Accelerator enabled, achieving 240 DMIPS (Dhrystone 2.1). This performance is sustained with zero wait states from Flash thanks to its 8 KB instruction cache. The core's 1.5 DMIPS/MHz efficiency and 651 CoreMark® score confirm deterministic real-time capability under full load.
Does this MCU support hardware-based secure boot and firmware authentication?
Yes. The STM32U575CGU3Q implements a hardware-rooted secure boot process using Arm TrustZone®, a secure hide protection area (HDP), and RDP (readout protection) levels. It supports Secure Firmware Installation (SFI) via embedded Root Secure Services (RSS) and complies with PSA Certified Level 3 requirements for secure boot integrity and anti-rollback enforcement.
What low-power modes are available, and what is the lowest achievable current draw?
It offers seven low-power modes: Shutdown (160 nA), Standby (210 nA), Standby+RTC (530 nA), Stop 3 (1.9 µA with 16 KB SRAM, 4.3 µA with full SRAM), and Stop 2 (4.0–8.95 µA depending on SRAM retention). All modes retain register content and support 24 configurable wake-up pins, enabling rapid resumption from deep sleep without full reinitialization.
Is the UCPD peripheral capable of full USB Type-C® Power Delivery negotiation?
Yes. The integrated UCPD (USB-C Power Delivery) controller handles complete PD 3.0 protocol stack execution-including BMC physical layer signaling, PD message parsing, policy engine, and VCONN switching-without CPU involvement. It supports sink/source roles, programmable PDOs, and Fast Role Swap, enabling self-contained USB-C port control in portable and docking applications.
STM32U575CGU3Q Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 48-UFQFN Exposed Pad
- Series:
- STM32U5
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 160MHz
- Connectivity:
- CANbus, I2C, IrDA, LINbus, SAI, SmartCard, SPDIF, SPI, UART/USART, USB, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
- Number of I/O:
- 33
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 784K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 10x12/14b SAR; D/A 2x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32U575CGU3Q FAQ
1.How can I place an order for STM32U575CGU3Q through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32U575CGU3Q on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32U575CGU3Q reliable?
The price and inventory of STM32U575CGU3Q are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32U575CGU3Q is usually 5 days.
3.What payment methods are accepted for STM32U575CGU3Q?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32U575CGU3Q transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32U575CGU3Q?
STM32U575CGU3Q orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32U575CGU3Q order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32U575CGU3Q?
For technical support, including STM32U575CGU3Q datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32U575CGU3Q requirements.
6.How does Aetrix verify that STM32U575CGU3Q is sourced from the original manufacturer or authorized distributors?
All STM32U575CGU3Q products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32U575CGU3Q meets industry standards.
7.What is the process for return or replacement of STM32U575CGU3Q?
All STM32U575CGU3Q units undergo pre-shipment inspection (PSI). If there is an issue with STM32U575CGU3Q, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32U575CGU3Q part is unused and in its original packaging.
Return procedure for STM32U575CGU3Q:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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