STMicroelectronics STM32U585CIU6TR

Overview

STM32U585CIU6TR from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit microcontroller with TrustZone® security, FPU, and 240 DMIPS performance. It integrates 2 MB Flash (with ECC), 786 KB SRAM, dual AES coprocessors, PSA Level 3/SESIP3 certification, and supports LPBAM autonomous peripheral operation down to Stop 2 mode. It targets secure, battery-powered IoT edge nodes requiring real-time sensing, encrypted telemetry, and long-term operation on coin-cell or energy-harvested power.

For engineers reviewing the STM32U585CIU6TR datasheet, STM32U585CIU6TR pinout, STM32U585CIU6TR application, or STM32U585CIU6TR equivalent, key selection considerations include its 160 nA Shutdown mode, 530 nA Standby-with-RTC current, TrustZone-enforced memory isolation, Octo-SPI on-the-fly decryption, and 14-bit ADC with hardware oversampling for sensor fusion in constrained environments.

Technical Context

The device implements a dual-bank Arm Cortex-M33 core with TrustZone-enabled secure/non-secure world separation, MPU, DSP extensions, and single-precision FPU. Its ART Accelerator includes 8 KB instruction cache and 4 KB data cache, enabling zero-wait-state execution at up to 160 MHz from Flash or external memories.

Power architecture combines embedded LDO and SMPS step-down converter with dynamic voltage scaling and switch-on-the-fly capability. Low-power modes are hierarchically structured: Shutdown (160 nA), Standby (210 nA), Stop 2 (4.0 µA with 16 KB SRAM), and Stop 3 (1.9 µA with 16 KB SRAM), all supporting LPBAM-driven DMA-peripheral autonomy without CPU wake-up.

Key Specifications

Pinout & Package

STM32U585CIU6TR is packaged in UFQFPN48 (7 × 7 mm, 0.5 mm pitch), a compact, thermally enhanced surface-mount package suitable for space-constrained portable and wearable designs. Pin count and I/O mapping align with the UFBGA132 and LQFP100 variants but optimized for minimal PCB footprint and simplified routing.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.

Compared with STM32L562VEJ6, the STM32U585CIU6TR adds on-the-fly external memory decryption and hardware math accelerators for sensor fusion, while versus LPC55S69JBD100 it delivers superior ultra-low-power metrics and formal PSA Level 3 assurance for regulated deployments.

Availability

STM32U585CIU6TR is available at Aetrix Electronics and suitable for smart utility meters, wearable health monitors, industrial wireless sensor nodes, and secure edge gateways requiring stable component supply across multi-year production cycles.

Supply support for STM32U585CIU6TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive semiconductors since 1987.

The STM32U5 series is ST's flagship ultra-low-power secure MCU line, engineered specifically for battery-operated IoT endpoints demanding PSA-certified security, sub-µA sleep currents, and integrated analog/motor/audio peripherals without external support components.

FAQ

What is the maximum operating frequency and associated DMIPS rating?

The STM32U585CIU6TR operates at up to 160 MHz with an ART Accelerator-enabled performance of 240 DMIPS. This is measured using Dhrystone 2.1 benchmark and confirmed in ST's DS13086 Rev 10 datasheet Section 2.2. The core achieves 1.5 DMIPS/MHz efficiency due to instruction/data caching and branch prediction.

Does this MCU support secure firmware updates over-the-air (OTA)?

Yes - the device supports secure OTA updates via TF-M (Trusted Firmware-M) integration, leveraging its PSA Level 3 certification, hardware unique key (HUK), secure hide protection area (HDP), and dual AES coprocessors. Signed firmware images are validated before execution, and decrypted in-place using OTFDEC for external memory.

What are the key differences between Stop 2 and Stop 3 low-power modes?

Stop 2 retains 16 KB or full 786 KB SRAM content and supports LPBAM peripherals; typical current is 4.0 µA (16 KB) or 8.95 µA (full SRAM). Stop 3 retains only 16 KB SRAM and disables more clocks; current drops to 1.9 µA (16 KB) or 4.3 µA (full SRAM). Both modes allow wake-up via EXTI, RTC alarm, or LPDMA completion.

Which analog peripherals remain functional in Stop 2 mode?

In Stop 2 mode, ADC4 (12-bit, 2.5-Msps) operates autonomously with hardware oversampling, along with comparators, op-amps, and the temperature sensor. These can trigger LPDMA transfers and wake the system - enabling continuous sensor monitoring without CPU involvement or full SRAM retention.