STMicroelectronics STM32U595AIH6Q

Overview

STM32U595AIH6Q from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit MCU with TrustZone® and FPU, delivering 240 DMIPS at up to 160 MHz. It integrates 4 MB Flash with ECC, 2.5 MB SRAM (with configurable ECC), LTDC, MIPI® DSI host controller, Neo-Chrom GPU, and dual 14-bit ADCs - deployed in battery-powered industrial HMI, secure IoT edge nodes, and portable medical displays.

For engineers reviewing the STM32U595AIH6Q datasheet, STM32U595AIH6Q pinout, STM32U595AIH6Q application, or STM32U595AIH6Q equivalent, key selection criteria include TrustZone-enabled secure boot, sub-µA Stop 3 mode with 2.5-MB SRAM retention, MIPI DSI lane timing compliance (500 Mbit/s), and dual independent analog subsystems supporting autonomous operation in Stop 2 mode.

Technical Context

The STM32U595AIH6Q implements a dual-bank Flash architecture with read-while-write capability and hardware ECC, enabling secure over-the-air firmware updates without runtime interruption. Its power architecture combines embedded LDO and SMPS step-down converter with dynamic voltage scaling and FlexPowerControl, allowing on-the-fly switching between regulators for optimal efficiency across operating modes.

TrustZone® is implemented at silicon level with GTZC (Global TrustZone Controller), securable peripherals, memory regions, and I/Os - supporting secure boot via unique entry point and HDP (Hide Protection Area). The Neo-Chrom GPU and Chrom-ART Accelerator (DMA2D) operate independently of the CPU, enabling concurrent UI rendering and application processing under low-power constraints.

Key Specifications

Pinout & Package

LQFP100 (14 × 14 mm, 0.5 mm pitch) package with 100 pins. Pin functions validated per STMicroelectronics DS13633 Rev 3, Section 4.2 (Pin description) and Table 17 (Pinout schematics).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.

Compared with STM32U575ZIT6, the STM32U595AIH6Q adds MIPI DSI, LTDC, and GPU2D for embedded displays while doubling Flash/SRAM; versus i.MX RT1187, it delivers superior hardware-rooted TrustZone enforcement and lower static power, making it optimal for certified medical and industrial safety-critical UIs.

Availability

STM32U595AIH6Q is available at Aetrix Electronics and suitable for industrial HMI, secure IoT edge nodes, and portable medical devices requiring stable component supply, long-term lifecycle assurance, and full traceability through ST's qualified manufacturing lines.

Supply support for STM32U595AIH6Q includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and automotive-grade components since 1987.

The STM32U5 series targets ultra-low-power, security-critical embedded applications - engineered to meet PSA Certified Level 3 and SESIP certification requirements while enabling rich graphics and wireless connectivity in constrained energy environments.

FAQ

What is the maximum operating temperature range for STM32U595AIH6Q?

The STM32U595AIH6Q is rated for industrial operation from –40 °C to +125 °C ambient temperature, verified per DS13633 Rev 3 Section 5.3.1. This extended range supports deployment in harsh environments such as factory automation controllers and outdoor energy infrastructure without derating.

Does STM32U595AIH6Q support hardware-accelerated cryptography beyond AES?

Yes - it integrates HASH (SHA-1/SHA-224/SHA-256), TRNG compliant with NIST SP800-90B, and secure key storage in 512-byte OTP and HDP. CORDIC and FMAC accelerate elliptic curve and filter math, but no dedicated RSA/ECC accelerator is present; those operations rely on optimized software libraries leveraging TrustZone-protected memory.

Can the MIPI DSI interface drive a 1080p display at 60 Hz?

No - the dual-lane MIPI DSI interface supports up to 500 Mbit/s per lane (1 Gbit/s aggregate), which limits practical resolution to ~720p@60 Hz or 1080p@30 Hz depending on pixel format and blanking intervals. For 1080p@60 Hz, external DSI bridge ICs or parallel LTDC interface with external timing controller are required.

Is the 2.5 MB SRAM fully accessible in all low-power modes?

No - only 40 KB of SRAM remains powered in Stop 3 mode (2 µA), while full 2.5 MB retention requires Stop 3 with SMPS active (8.2 µA). In Shutdown mode (150 nA), only 2 KB backup SRAM and RTC registers retain state. SRAM3 partitioning and ECC configuration further affect usable capacity in low-power states.