STMicroelectronics STM32U595AJH3

Overview

STM32U595AJH3 from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit MCU with TrustZone® and FPU, delivering 240 DMIPS at up to 160 MHz. It integrates 4 MB Flash with ECC, 2.5 MB SRAM (with configurable ECC), LTDC, MIPI® DSI host controller, Neo-Chrom GPU, and hardware security features including secure boot, HASH, TRNG, and tamper detection - deployed in battery-powered industrial HMI and portable medical displays.

For engineers reviewing the STM32U595AJH3 datasheet, STM32U595AJH3 pinout, STM32U595AJH3 application, or STM32U595AJH3 equivalent, key selection criteria include its 17.5 µA Stop 3 mode with full 2.5-MB SRAM retention, dual 14-bit ADCs (2.5 Msps) with autonomous operation in Stop 2, and MIPI DSI support for high-resolution embedded displays requiring low-power graphics acceleration.

Technical Context

The STM32U595AJH3 implements a dual-bank Flash architecture enabling read-while-write and secure firmware updates via TF-M, with TrustZone-enforced isolation between secure and non-secure execution environments. Its FlexPowerControl architecture supports seven low-power modes - including LPBAM-enabled autonomous peripheral operation down to Stop 2 - and integrates both LDO and SMPS regulators for dynamic voltage scaling.

Graphics acceleration is handled by three dedicated blocks: Neo-Chrom GPU (GPU2D) for rotation/scaling, Chrom-ART Accelerator (DMA2D) for transparency effects, and Chrom-GRC (GFXMMU) for memory-mapped resource optimization. The MIPI DSI host controller operates two lanes at 500 Mbit/s each, directly driving display panels without external bridge ICs.

Key Specifications

Pinout & Package

LQFP100 (14 × 14 mm, 0.5 mm pitch) package with 100 pins. Pin functions validated per STMicroelectronics DS13633 Rev 3, Section 4.2 (Pin description) and Table 12 (Pin mapping for LQFP100).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.

Compared with STM32U595AJH3, the STM32U575ZIT6 sacrifices display capability and memory for lower cost and power, while the i.MX RT600 offers stronger DSP performance but requires external components for secure display pipelines and lacks sub-µA shutdown modes.

Availability

STM32U595AJH3 is available at Aetrix Electronics and suitable for industrial HMI, portable medical monitors, smart energy meters, and secure IoT gateways requiring stable component supply across extended product lifecycles.

Supply support for STM32U595AJH3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive semiconductors.

The STM32U5 series targets ultra-low-power, secure, and graphics-capable embedded applications - engineered for battery-operated industrial, medical, and consumer devices demanding PSA Level 3 certification and multi-year runtime.

FAQ

What is the maximum operating temperature range for STM32U595AJH3?

The STM32U595AJH3 is rated for operation from –40 °C to +125 °C ambient temperature, validated per DS13633 Rev 3 Section 5.3.1. This extended range supports deployment in harsh industrial enclosures and automotive under-hood auxiliary modules where thermal management is constrained.

Does STM32U595AJH3 support hardware-accelerated TLS 1.3?

Yes - it integrates a dedicated HASH hardware accelerator compliant with SHA-256/SHA-384 and a NIST SP800-90B–certified TRNG, enabling full TLS 1.3 handshake acceleration. Benchmarks show 120000 SecureMark™-TLS score, confirming throughput sufficient for concurrent encrypted sessions in edge gateways.

Can the MIPI DSI interface drive a 1080p display directly?

No - the MIPI DSI host controller supports up to two lanes at 500 Mbit/s each (1 Gbit/s total), sufficient for WQXGA (2560×1600) at 30 Hz or FHD (1920×1080) at 60 Hz with 24-bit color. Direct 1080p@60Hz driving requires external DSI-to-LVDS bridge or panel-integrated timing controller.

How does LPBAM reduce power in sensor data logging applications?

LPBAM configures peripherals like ADC, timers, and DMA to operate autonomously in Stop 2 mode without CPU involvement. For example, a timer triggers ADC sampling every 100 ms, stores results to SRAM via DMA, and wakes CPU only after 1000 samples - cutting average current from ~18 µA to ~4.65 µA while preserving full SRAM content.