STMicroelectronics STM32U595AJH3Q

Overview

STM32U595AJH3Q from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit microcontroller with TrustZone® security, 240 DMIPS performance at 160 MHz, 4 MB Flash with ECC, and 2.5 MB SRAM (ECC configurable). It integrates LTDC, MIPI® DSI host controller, Neo-Chrom GPU, and dual 14-bit ADCs-designed for secure, graphics-rich IoT edge devices operating in -40 °C to +125 °C industrial environments.

For engineers reviewing the STM32U595AJH3Q datasheet, STM32U595AJH3Q pinout, STM32U595AJH3Q application, or STM32U595AJH3Q equivalent, key selection criteria include TrustZone-enabled secure boot, LPBAM autonomous peripheral operation down to Stop 2 mode, 150 nA Shutdown current, 2.5 MB on-chip SRAM with configurable ECC, and dual DSI lane support up to 500 Mbit/s for high-resolution display interfaces.

Technical Context

The device implements Arm TrustZone for hardware-enforced isolation between secure and non-secure firmware execution, with dedicated GTZC (Global TrustZone Controller) managing memory, peripheral, and I/O security attribution. Its FlexPowerControl architecture enables dynamic voltage scaling via integrated SMPS and LDO, supporting five low-power modes including Stop 2 with autonomous ADC/DAC operation and 480 nA Standby with RTC.

Core peripherals include a 160 MHz-capable ART Accelerator with 32 KB ICACHE and dual 16 KB DCACHEs (for external memory and graphics), Neo-Chrom GPU2D for rotation/scaling, Chrom-ART DMA2D for transparency effects, and Chrom-GRC GFXMMU for 20% graphic resource optimization-enabling efficient TFT-LCD and MIPI-DSI display pipelines without CPU load.

Key Specifications

Pinout & Package

STM32U595AJH3Q is housed in a 132-pin UFBGA package (7 × 7 mm, 0.5 mm pitch) with 111 user I/Os, including 14 low-voltage I/Os (1.08 V supply), most 5 V-tolerant, and 24 wake-up capable pins. The package supports full peripheral mapping for MIPI DSI, LTDC, Octo-SPI, and dual ADC/DAC channels.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.

Compared with STM32U575ZIT6, the STM32U595AJH3Q delivers 2× Flash/SRAM and full MIPI DSI+LTDC+GPU graphics acceleration - essential for rich HMI. Against LPC55S69JBD100, it offers superior memory scalability, certified ultra-low-power modes, and hardware-secured display data paths - critical for industrial UI and long-life battery designs.

Availability

STM32U595AJH3Q is available at Aetrix Electronics and suitable for smart industrial HMIs, secure edge gateways, battery-powered medical monitors, and ultra-low-power smart meters requiring stable component supply across extended product lifecycles.

Supply support for STM32U595AJH3Q includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive semiconductors since 1987.

The STM32U5 series is ST's flagship ultra-low-power secure MCU line targeting industrial IoT, medical wearables, and smart energy applications - engineered to deliver best-in-class ULPMark™ scores, PSA Certified Level 3 security, and integrated graphics acceleration without external components.

FAQ

What is the maximum operating temperature for STM32U595AJH3Q?

The STM32U595AJH3Q is rated for operation from –40 °C to +125 °C ambient temperature, validated per industrial-grade specifications in DS13633 Rev 3. This extended range supports deployment in harsh environments such as motor drives, smart grid equipment, and under-hood automotive modules where thermal stability is critical.

Does STM32U595AJH3Q support external memory interfaces beyond Octo-SPI?

Yes - in addition to two Octo-SPI controllers, it features a 16-bit HSPI interface (up to 160 MHz), Flexible Static Memory Controller (FSMC) for SRAM/PSRAM/NOR/NAND/FRAM, and dual SDMMC interfaces. These enable direct attachment of external display frame buffers, high-density code storage, and removable media - eliminating need for external memory controllers.

How does TrustZone implementation differ between STM32U595AJH3Q and earlier STM32L5 devices?

The STM32U595AJH3Q enhances TrustZone with Global TrustZone Controller (GTZC) supporting dynamic peripheral attribution, securable I/Os, and HDP (Hide Protection Area) for immutable secure boot code. Unlike STM32L5, it adds secure firmware installation (SFI) with embedded Root Secure Services (RSS), enabling field-upgradable secure images without external secure elements or pre-provisioning steps.

Can the Neo-Chrom GPU operate independently of the CPU during low-power modes?

No - the Neo-Chrom GPU requires active CPU and clock domain operation; it does not function in Stop or Standby modes. However, the Chrom-ART DMA2D accelerator can execute predefined 2D operations autonomously in Run and Sleep modes, and LPBAM enables background DMA transfers that feed GPU input buffers without CPU intervention - reducing effective CPU utilization by up to 65% in UI refresh cycles.