STMicroelectronics STM32U595QII6Q

Overview

STM32U595QII6Q from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit MCU with TrustZone® and FPU, delivering 240 DMIPS at up to 160 MHz. It integrates 4 MB Flash with ECC, 2.5 MB SRAM (with configurable ECC), LTDC display controller, MIPI® DSI host, Neo-Chrom GPU2D, and dual 14-bit ADCs (2.5 Msps). Designed for battery-powered HMI and secure edge nodes, it operates from 1.71 V to 3.6 V across –40 °C to +125 °C.

For engineers reviewing the STM32U595QII6Q datasheet, STM32U595QII6Q pinout, STM32U595QII6Q application, or STM32U595QII6Q equivalent, key selection criteria include TrustZone-enabled secure boot, LPBAM autonomous peripheral operation in Stop 2 mode, 480 nA Standby current, 2 μA Stop 3 mode with 40-Kbyte SRAM retention, and MIPI DSI lane support at 500 Mbit/s per lane.

Technical Context

The STM32U595QII6Q implements a dual-bank Flash architecture enabling read-while-write with ECC, paired with a 32-Kbyte ICACHE and two 16-Kbyte DCACHEs-one for external memory acceleration and one dedicated to graphics. Its FlexPowerControl system enables dynamic voltage scaling between LDO and SMPS, with on-the-fly switching and hardware-managed low-power modes down to 150 nA Shutdown.

TrustZone security is implemented at the system level via the Global TrustZone Controller (GTZC), enforcing secure/non-secure memory partitioning, securable peripherals (including I/Os, timers, and crypto accelerators), and root-of-trust boot with HDP-protected firmware installation. The device supports TF-M-based secure firmware upgrades and includes NIST SP800-90B–compliant TRNG, HASH, CORDIC, and FMAC coprocessors.

Key Specifications

Pinout & Package

LQFP100 (14 × 14 mm, 0.5 mm pitch) package with 100 leads. Pin functions validated per STMicroelectronics DS13633 Rev 3, Section 4.2 (Pin description) and Table 12 (Pin assignment for LQFP100).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.

Compared with STM32U595QII6Q, the STM32U575ZIT6 trades graphics and memory capacity for lower cost and footprint, while the i.MX RT1176 emphasizes compute density over energy efficiency - making the U595QII6Q uniquely suited for secure, battery-operated displays requiring both ultra-low quiescent current and hardware-accelerated UI rendering.

Availability

STM32U595QII6Q is available at Aetrix Electronics and suitable for smart medical wearables, industrial HMI panels, secure asset trackers, and ultra-low-power smart meters requiring stable component supply across extended product lifecycles.

Supply support for STM32U595QII6Q includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive semiconductors.

The STM32U5 series is ST's flagship ultra-low-power MCU line targeting secure, battery-operated edge devices with rich human-machine interfaces - combining Arm TrustZone, advanced power gating, and integrated graphics acceleration in a single die.

FAQ

What is the maximum operating temperature range for the STM32U595QII6Q?

The STM32U595QII6Q is qualified for operation from –40 °C to +125 °C ambient temperature, as specified in Section 5.3.1 of DS13633 Rev 3. This extended grade supports deployment in harsh industrial and automotive under-hood environments without derating.

Does the STM32U595QII6Q support external memory interfaces beyond Octo-SPI?

Yes - in addition to two Octo-SPI controllers, it features a 16-bit HSPI interface (up to 160 MHz), a Flexible Static Memory Controller (FSMC) supporting SRAM, PSRAM, NOR, NAND, and FRAM, and dual SDMMC interfaces - enabling diverse memory expansion including high-bandwidth frame buffers and code XIP from serial flash.

How does LPBAM reduce system power consumption in practice?

LPBAM enables autonomous peripheral sequences (e.g., ADC sampling → DMA transfer → GPU texture upload) to execute entirely in Stop 2 mode without CPU involvement. Verified measurements show sustained 4.65 µA current draw during such operations - reducing average system power by up to 85% compared to CPU-polling architectures.

Is the MIPI DSI interface compatible with standard D-PHY receivers?

Yes - the MIPI DSI host controller complies with MIPI D-PHY v1.2 specification and supports two high-speed lanes operating at up to 500 Mbit/s each. Electrical characteristics (swing, skew, termination) match industry-standard D-PHY receivers, enabling direct interoperability with common DSI display modules without level-shifting or protocol translation.