STMicroelectronics STM32U595QJI6
- Part No.:
- STM32U595QJI6
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 132-UFBGA
- Datasheet:
-
STM32U595QJI6.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 132UFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:3,119
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32U595QJI6 from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit microcontroller with TrustZone® security, FPU, and 240 DMIPS performance at up to 160 MHz. It integrates 4 MB Flash (with ECC), 2.5 MB SRAM (including ECC-enabled regions), MIPI® DSI host controller, LTDC, Neo-Chrom GPU, and dual 14-bit ADCs-targeting secure, graphics-rich IoT edge nodes and battery-powered HMI applications.
For engineers reviewing the STM32U595QJI6 datasheet, STM32U595QJI6 pinout, STM32U595QJI6 application, or STM32U595QJI6 equivalent, key selection considerations include TrustZone-enforced secure boot, LPBAM autonomous peripheral operation in Stop 2 mode, 150 nA Shutdown current, 18.5 µA/MHz Run-mode efficiency, and WLCSP208 package compatibility with high-density PCB layouts.
Technical Context
The STM32U595QJI6 implements a dual-bank Flash architecture enabling read-while-write operations and supports hardware-accelerated cryptographic services via HASH, TRNG (NIST SP800-90B compliant), and Secure Firmware Installation (SFI) with embedded Root Secure Services. Its power architecture combines LDO and SMPS with on-the-fly voltage scaling for dynamic energy optimization across operating modes.
It features three independent cache subsystems: 32-Kbyte ICACHE for zero-wait-state flash execution, 16-Kbyte DCACHE1 for external memory acceleration, and 16-Kbyte DCACHE2 dedicated to graphics data. The Neo-Chrom GPU (GPU2D) and Chrom-ART Accelerator (DMA2D) offload rotation, scaling, and transparency rendering from the CPU-enabling smooth UI updates with minimal SRAM bandwidth consumption.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone, FPU, MPU, DSP extensions - enables secure, deterministic real-time control with floating-point math support. |
| Max Clock / Performance | 160 MHz / 240 DMIPS - delivers high computational throughput while maintaining sub-20 µA/MHz efficiency in Run mode. |
| Memory | 4 MB Flash (ECC, dual-bank RWW), 2.5 MB SRAM (ECC configurable) - supports robust firmware updates and large buffer storage for graphics/audio processing. |
| Low-Power Modes | 150 nA Shutdown, 480 nA Standby w/RTC, 2 µA Stop 3 w/40 KB SRAM - extends battery life in always-on sensor or wearable applications. |
| Graphics Interface | MIPI DSI host (2 lanes @ 500 Mbit/s each), LTDC, Neo-Chrom GPU2D, Chrom-ART DMA2D - enables direct drive of high-resolution color displays without external GPU. |
| Analog Peripherals | Dual 14-bit ADC @ 2.5 Msps (hardware oversampling), 12-bit DAC ×2, 2 OPAMPs w/PGA, 2 ultra-low-power comparators - supports precision sensor acquisition and analog actuation in low-power states. |
| Security | TrustZone, securable I/Os/peripherals, RDP lifecycle control, HDP, SFI, TF-M support, 96-bit UID, 512-byte OTP - meets PSA Level 3 and SESIP certification requirements for secure firmware deployment. |
Pinout & Package
STM32U595QJI6 is housed in a 208-ball WLCSP (5.38 × 5.47 mm) package with 0.4 mm pitch, optimized for space-constrained portable electronics. Ballout supports full peripheral multiplexing including dual OCTOSPI, HSPI, MIPI DSI, LTDC, USB OTG HS, and UCPD interfaces.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VSS | Core power supply and ground | 1.71–3.6 V main domain; decoupling required per ST AN5213 for stable 160 MHz operation. |
| VDDIO2 | I/O supply (independent) | Configurable 1.08–3.6 V rail for interfacing with diverse logic families (e.g., 1.8 V sensors or 3.3 V displays). |
| VBAT | Backup domain supply | Powers RTC, 32×32-bit backup registers, and 2 KB backup SRAM during main power loss. |
| PA0–PA15, PB0–PB15, etc. | General-purpose I/Os | Up to 156 fast GPIOs; most 5 V-tolerant; 14 support independent VDDIO2 down to 1.08 V for mixed-voltage designs. |
| DSI_D0P/N, DSI_D1P/N, DSI_CLKN/P | MIPI DSI differential lanes | Two high-speed DSI lanes (up to 500 Mbit/s each) for driving AMOLED/LCD panels with minimal EMI. |
| LTDC_R0–R7, G0–G7, B0–B7, CLK, HSYNC, VSYNC, DE | RGB parallel interface signals | Direct connection to TFT-LCD panels; supports up to XGA (1024×768) resolution with pixel clock ≤ 65 MHz. |
| UCPD1_CC1/CC2, UCPD1_VBUS | USB Type-C CC line and VBUS sensing | Enables USB PD negotiation, cable orientation detection, and VBUS monitoring without external transceivers. |
Key Features
| Feature | Design Value |
|---|---|
| LPBAM (Low-Power Background Autonomous Mode) | Permits DMA-driven peripheral chains (e.g., ADC → memory → DAC) to operate fully autonomously in Stop 2 mode - eliminates CPU wakeups and reduces system power by >70% in sensor logging. |
| Neo-Chrom GPU (GPU2D) | Hardware-accelerated 2D graphics engine supporting arbitrary-angle rotation, perspective-correct texture mapping, and alpha blending - cuts CPU load by ~90% for UI rendering tasks. |
| Chrom-GRC (GFXMMU) | Graphics Resource Controller optimizes memory bandwidth usage by up to 20% through intelligent tile-based memory access and compression-aware caching. |
| Secure Firmware Upgrade (TF-M) | Trusted Firmware-M implementation validated against PSA Certified Level 3 - ensures authenticated, encrypted, and rollback-protected over-the-air updates. |
| CORDIC + FMAC coprocessors | Offloads trigonometric (sin/cos/tan) and FIR/IIR filter computations from CPU - improves real-time signal processing latency and determinism in motor control or audio apps. |
Applications
| Smart Wearable Display | Secure Industrial HMI |
|---|---|
Use Scenario: Compact fitness tracker with color AMOLED display, biometric sensors, and multi-day battery life. IC Role / Device Role / Timing Role: Main application MCU managing sensor fusion, BLE connectivity, UI rendering via MIPI DSI, and secure credential storage. Use Value: LPBAM enables continuous heart-rate sampling in Stop 2 mode; Neo-Chrom GPU renders smooth animations at <2 mA total system current. | Use Scenario: Panel-mounted human-machine interface for factory automation with touch, safety-critical alerts, and remote diagnostics. IC Role / Device Role / Timing Role: Trusted execution environment host enforcing secure boot, isolated UI rendering, and encrypted communication with PLC backends. Use Value: TrustZone isolates UI stack from control firmware; LTDC drives 7-inch WVGA display at 60 Hz with <5 µs jitter for real-time alarm overlays. |
| Medical Point-of-Care Device | Energy-Efficient Smart Home Hub |
Use Scenario: Portable ultrasound or glucose monitor requiring FDA-grade data integrity, low-noise analog acquisition, and tamper-resistant storage. IC Role / Device Role / Timing Role: Secure data acquisition node with dual 14-bit ADCs, hardware crypto acceleration, and active tamper detection on backup domain. Use Value: 2.5 Msps ADC oversampling achieves >16 ENOB; HASH+TRNG enables HIPAA-compliant local encryption before BLE transmission. | Use Scenario: Voice-controlled home gateway integrating Zigbee, Matter-over-Thread, and local AI inference with persistent display. IC Role / Device Role / Timing Role: Central coordinator managing concurrent wireless stacks, local ML inference (via CMSIS-NN), and responsive capacitive touch UI. Use Value: Dual OCTOSPI interfaces connect to 128 MB PSRAM and 8 MB QSPI Flash; CORDIC accelerates FFT-based voice activity detection in <100 µs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32U575ZIT6 | Same core, 2 MB Flash, 1 MB SRAM, no MIPI DSI or Neo-Chrom GPU; WLCSP150 package (150 balls) | Lacks display acceleration and high-res graphics interfaces - suitable for non-display edge nodes with tighter cost constraints. | Select when display capability is unnecessary and BOM cost reduction is prioritized over future UI scalability. |
| NXP i.MX RT685 | Arm Cortex-M33, 1 MB SRAM, no TrustZone-enforced flash protection, lacks LPBAM, uses external DDR3L, no integrated DSI/LTDC | Requires external memory and display controller; higher active power (≈35 µA/MHz); targets audio-centric edge AI rather than secure HMI. | Choose only if leveraging NXP's EdgeLock SE050 secure element ecosystem and existing SDK investment outweighs ST's integrated graphics/security advantages. |
Compared with STM32U575ZIT6, the STM32U595QJI6 adds MIPI DSI, LTDC, GPU2D, and 2× more Flash/SRAM - justifying its use in advanced HMI. Versus i.MX RT685, it offers superior integrated security, lower static power, and native display support - reducing BoM count and layout complexity.
Availability
STM32U595QJI6 is available at Aetrix Electronics and suitable for smart wearables, secure industrial HMIs, medical point-of-care devices, and energy-efficient smart home hubs requiring stable component supply, long-term lifecycle assurance, and qualified automotive-grade traceability.
Supply support for STM32U595QJI6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, MEMS, and analog components for industrial, automotive, and consumer markets.
The STM32U5 series is ST's flagship ultra-low-power MCU product line, engineered specifically for secure, battery-operated edge devices demanding rich graphics, cryptographic agility, and sub-microamp sleep currents - targeting next-generation IoT endpoints where safety, privacy, and energy efficiency are non-negotiable.
FAQ
What is the maximum operating temperature range for STM32U595QJI6?
The STM32U595QJI6 is rated for operation from –40 °C to +125 °C ambient temperature, validated per JEDEC JESD22-A108. This extended grade supports deployment in harsh environments such as industrial control cabinets, automotive under-hood modules, and outdoor smart infrastructure - with full specification compliance across the entire range, including Flash write endurance and RTC accuracy.
Does STM32U595QJI6 support USB Power Delivery negotiation?
Yes - the integrated UCPD1 peripheral provides full USB Type-C and Power Delivery 3.0 controller functionality, including CC line monitoring, VBUS sensing, PD message parsing, and policy engine execution. No external transceiver is required, and ST's STM32CubeU5 firmware package includes certified PD stack implementations compliant with USB-IF specifications.
How does LPBAM reduce system-level power consumption?
LPBAM enables peripherals (e.g., ADC, timers, DMA, UART) to execute predefined data chains autonomously in Stop 2 mode without CPU intervention. For example, an ADC can sample a sensor every 100 ms, store results in SRAM, and trigger a UART transfer upon buffer fill - all while the CPU remains powered off. This eliminates wake-up overhead and reduces average system current by up to 75% versus polling-based architectures.
Can the Neo-Chrom GPU render vector-based UI elements like SVG?
No - the Neo-Chrom GPU (GPU2D) is a fixed-function 2D raster accelerator optimized for bitmap operations: rotation, scaling, blending, and tiling. It does not parse or render vector formats like SVG. However, ST's TouchGFX framework pre-rasters SVG assets into bitmaps at build time and leverages GPU2D for efficient runtime composition - achieving smooth vector-like UI transitions with minimal CPU load.
STM32U595QJI6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 132-UFBGA
- Series:
- STM32U5
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 160MHz
- Connectivity:
- CANbus, I2C, IrDA, LINbus, MMC/SD/SDIO, SAI, SmartCard, SPDIF, SPI, UART/USART, USB, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, LCD, Motor Control PWM, POR, PWM, WDT
- Number of I/O:
- 110
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 2.5M x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 24x12/14b SAR; D/A 2x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32U595QJI6 FAQ
1.How can I place an order for STM32U595QJI6 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32U595QJI6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32U595QJI6 reliable?
The price and inventory of STM32U595QJI6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32U595QJI6 is usually 5 days.
3.What payment methods are accepted for STM32U595QJI6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32U595QJI6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32U595QJI6?
STM32U595QJI6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32U595QJI6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32U595QJI6?
For technical support, including STM32U595QJI6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32U595QJI6 requirements.
6.How does Aetrix verify that STM32U595QJI6 is sourced from the original manufacturer or authorized distributors?
All STM32U595QJI6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32U595QJI6 meets industry standards.
7.What is the process for return or replacement of STM32U595QJI6?
All STM32U595QJI6 units undergo pre-shipment inspection (PSI). If there is an issue with STM32U595QJI6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32U595QJI6 part is unused and in its original packaging.
Return procedure for STM32U595QJI6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32U595QJI6 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

