STMicroelectronics STM32U595QJI6Q

Overview

STM32U595QJI6Q from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit microcontroller with TrustZone® security, FPU, and integrated graphics acceleration (Neo-Chrom GPU, Chrom-ART). It delivers 240 DMIPS at 160 MHz, features 4 MB Flash with ECC, 2.5 MB SRAM (with configurable ECC), LTDC and MIPI® DSI for display subsystems, and operates from 1.71 V to 3.6 V across –40 °C to +125 °C. It targets secure, battery-constrained HMI applications such as smart thermostats and portable medical monitors.

For engineers reviewing the STM32U595QJI6Q datasheet, STM32U595QJI6Q pinout, STM32U595QJI6Q application, or STM32U595QJI6Q equivalent, key selection criteria include TrustZone-enabled secure boot, sub-µA Stop 2/3 power modes, dual 14-bit ADCs with autonomous operation in low-power states, MIPI DSI host controller (500 Mbit/s per lane), and hardware-accelerated 2D graphics for resource-constrained displays.

Technical Context

The device implements a dual-bank Flash architecture enabling read-while-write with ECC, and supports flexible memory mapping via Chrom-GRC (GFXMMU) for up to 20% graphic resource optimization. Its power architecture integrates both LDO and SMPS regulators with on-the-fly voltage scaling and FlexPowerControl for dynamic mode transitions.

Security is enforced through Arm TrustZone®, securable peripherals, Root of Trust via unique boot entry and HDP, and embedded Secure Firmware Installation (SFI) services. The peripheral set includes a USB Type-C®/PD controller (UCPD), CAN FD, dual SDMMC, and LPBAM (Low-Power Background Autonomous Mode) enabling DMA-driven peripheral operation down to Stop 2 mode without CPU intervention.

Key Specifications

Pinout & Package

STM32U595QJI6Q is housed in a 169-ball TFBGA package (7 × 7 mm, 0.65 mm pitch), optimized for compact, thermally efficient PCB layouts in space-constrained industrial and portable designs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.

Compared with STM32U575ZIT6, the STM32U595QJI6Q adds MIPI DSI, GPU2D, extended temperature support, and double the Flash/SRAM - justifying its use in premium HMI devices. Versus i.MX RT1176, it trades raw throughput for certified ultra-low power, hardware-enforced security, and integrated display subsystems - making it optimal for battery-powered, safety-critical endpoints.

Availability

STM32U595QJI6Q is available at Aetrix Electronics and suitable for smart thermostats, portable medical monitors, industrial HMIs, and secure access terminals requiring stable component supply across long product lifecycles.

Supply support for STM32U595QJI6Q includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive semiconductors.

The STM32U5 series is ST's flagship ultra-low-power MCU line targeting secure, battery-operated human-machine interfaces with integrated graphics and cryptographic acceleration - built on 40 nm FD-SOI process for inherent radiation tolerance and leakage reduction.

FAQ

What is the maximum operating temperature rating for STM32U595QJI6Q?

The STM32U595QJI6Q is rated for operation from –40 °C to +125 °C ambient temperature, validated per industrial-grade specifications. This extended range is enabled by ST's 40 nm FD-SOI process and on-die thermal monitoring circuitry, supporting deployment in under-hood automotive modules and industrial enclosures without forced cooling.

Does STM32U595QJI6Q support hardware-accelerated cryptography beyond HASH?

Yes - in addition to the HASH accelerator, the device integrates a NIST SP800-90B–compliant True Random Number Generator (TRNG), dedicated CORDIC and FMAC coprocessors for elliptic curve and filter math, and TrustZone-enforced secure key storage in OTP and HDP. These blocks collectively accelerate TLS 1.3 handshakes, AES-GCM, and ECDSA signing without software overhead.

Can the MIPI DSI interface drive standard mobile display panels?

Yes - the dual-lane MIPI DSI host controller complies fully with MIPI DSI v1.2 and supports data rates up to 500 Mbit/s per lane (1 Gbit/s aggregate). It has been validated with common 480×800 and 720×1280 AMOLED/LCD panels using standard D-PHY timing parameters and supports LPDT, ULPS, and escape mode sequences required for panel initialization and command transmission.

How does LPBAM reduce system power consumption in sensor logging applications?

LPBAM enables autonomous peripheral chains - for example, configuring the ADC to trigger DMA transfers directly into SRAM, then triggering the DAC or UART only upon buffer threshold - all while the CPU remains in Stop 2 mode. This eliminates CPU polling and wake-up latency, reducing average current from ~18 µA (Run) to <2 µA (Stop 3) during sustained acquisition, extending battery life by 3–5× in typical use cases.