STMicroelectronics STM32U595RIT6Q

Overview

STM32U595RIT6Q from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit MCU with TrustZone® and FPU, delivering 240 DMIPS at up to 160 MHz. It integrates 4 MB Flash (with ECC), 2.5 MB SRAM (including 322 KB with ECC), LTDC, MIPI® DSI host controller (2 lanes @ 500 Mbit/s each), Neo-Chrom GPU, and operates from 1.71 V to 3.6 V across –40 °C to +125 °C. It targets secure, graphics-rich IoT edge nodes requiring autonomous low-power operation.

For engineers reviewing the STM32U595RIT6Q datasheet, STM32U595RIT6Q pinout, STM32U595RIT6Q application, or STM32U595RIT6Q equivalent, key selection criteria include TrustZone-enabled secure boot, LPBAM peripheral autonomy in Stop 2 mode, 18.5 µA/MHz Run current at 3.3 V, 480 nA Stop 3 mode with 40-KB SRAM, and dual Octo-SPI interfaces for external memory expansion.

Technical Context

The STM32U595RIT6Q implements a dual-cache Arm Cortex-M33 core with ART Accelerator (32-KB ICACHE + 16-KB DCACHE1), enabling zero-wait-state execution from Flash at 160 MHz. Its FlexPowerControl architecture supports seven low-power modes - including Shutdown (150 nA), Standby (195 nA), and Stop 2/3 with configurable SRAM retention - all managed via embedded SMPS and LDO regulators with dynamic voltage scaling.

Security is enforced through hardware-enforced TrustZone partitioning, securable peripherals, Root of Trust via unique boot entry and HDP, and cryptographic acceleration via HASH, CORDIC, FMAC, and NIST SP800-90B–compliant TRNG. Graphics subsystem includes Neo-Chrom GPU2D, Chrom-ART DMA2D, and Chrom-GRC GFXMMU for resource-optimized rendering.

Key Specifications

Pinout & Package

LQFP64 (10 × 10 mm, 0.5 mm pitch) package with exposed thermal pad; 64 pins including 51 general-purpose I/Os (most 5V-tolerant), dual VDD/VSS pairs, dedicated VDDIO2 supply (1.08–3.6 V), VBAT, VREF+, VREF–, and debug interface (SWD).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.

Compared with STM32U575RIT6, the STM32U595RIT6Q adds MIPI DSI, GPU2D, and 2× SRAM - essential for display-centric designs; versus i.MX RT1187, it delivers 3.6× lower Stop 2 current and native TrustZone - critical for certified medical and industrial deployments.

Availability

STM32U595RIT6Q is available at Aetrix Electronics and suitable for smart wearables, secure industrial gateways, medical point-of-care terminals, and energy-harvested sensor networks requiring stable component supply, long-term lifecycle assurance, and qualified automotive-grade variants.

Supply support for STM32U595RIT6Q includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog devices for industrial, automotive, and consumer markets.

The STM32U5 series is ST's flagship ultra-low-power MCU product line, engineered specifically for secure, battery-operated edge AI and rich-display IoT endpoints demanding PSA-certified trust, sub-µA sleep, and integrated graphics acceleration.

FAQ

What is the maximum operating temperature rating for the STM32U595RIT6Q?

The STM32U595RIT6Q is qualified for operation from –40 °C to +125 °C ambient temperature, meeting industrial and extended-temperature requirements. This rating applies to the LQFP64 package under specified voltage and derating conditions per DS13633 Rev 3 Section 5.3.1. Thermal performance is validated with the exposed pad soldered to PCB copper for optimal heat dissipation.

Does the STM32U595RIT6Q support hardware-based secure boot with public-key verification?

Yes - it implements a hardware-rooted secure boot flow using immutable ROM code that verifies the signature of the first-stage bootloader (SB_SecureBoot) against ECDSA-P256 keys stored in the secure hide-protection area (HDP). The process enforces TrustZone isolation and prevents unsigned or tampered firmware execution, satisfying PSA Certified Level 3 requirements.

Can the MIPI DSI interface drive a 720p display at 60 Hz?

Yes - with two DSI lanes operating at 500 Mbit/s each (1 Gbps total), the interface supports up to 1.2 Gbps net bandwidth after encoding overhead. Driving a 720p (1280×720) RGB888 display at 60 Hz requires ≈990 Mbps, which falls within specification. Pixel clock generation and timing alignment are handled by the integrated DSI host controller and LTDC.

Is the 4-MB Flash memory organized in dual banks with read-while-write capability?

Yes - the 4-MB Flash is split into two independent banks (Bank 1 and Bank 2), each supporting concurrent read and write operations. This enables live firmware updates (e.g., background download to one bank while executing from the other) and eliminates application interruption during field upgrades, as confirmed in DS13633 Section 3.4.1 and RM0453 Section 3.4.3.