STMicroelectronics STM32U595RJT6

Overview

STM32U595RJT6 from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit MCU with TrustZone® and FPU, delivering 240 DMIPS at up to 160 MHz. It integrates 4 MB Flash with ECC, 2.5 MB SRAM (with configurable ECC), MIPI® DSI host controller, LTDC, Neo-Chrom GPU2D, and dual 14-bit ADCs (2.5 Msps). It targets secure, graphics-rich, battery-constrained applications such as smart wearables and industrial HMIs.

For engineers reviewing the STM32U595RJT6 datasheet, STM32U595RJT6 pinout, STM32U595RJT6 application, or STM32U595RJT6 equivalent, key selection criteria include TrustZone-enabled secure boot, LPBAM autonomous peripheral operation in Stop 2 mode, 150 nA Shutdown current, 160 MHz max CPU frequency with ART Accelerator, and MIPI DSI + LTDC coexistence for embedded display subsystems.

Technical Context

The STM32U595RJT6 implements a dual-cache Arm Cortex-M33 core with MPU, DSP extensions, and single-precision FPU, supported by 32 KB ICACHE and two 16 KB DCACHEs (DCACHE1 for external memory, DCACHE2 for graphics). Its FlexPowerControl architecture enables seven low-power modes - including Stop 2 with 4.65 µA (40 KB SRAM retained) and Shutdown at 150 nA - with full peripheral autonomy via LPBAM.

Security is enforced through hardware-rooted TrustZone®, securable peripherals, RDP-based life-cycle management, and embedded RSS for Secure Firmware Installation (SFI). Graphics acceleration combines Neo-Chrom GPU2D (rotation/scaling), Chrom-ART DMA2D (blending/composition), and Chrom-GRC (GFXMMU) for resource optimization - all operating under TrustZone-isolated execution contexts.

Key Specifications

Pinout & Package

LQFP64 (10 × 10 mm, 0.5 mm pitch) package with 51 general-purpose I/Os (most 5V-tolerant), 4 dedicated V_DDIO2 pins for independent 1.08–3.6 V I/O supply, and dedicated power/ground pairs for analog, digital, and VBAT domains.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.

Compared with STM32U575ZIT6, the STM32U595RJT6 adds MIPI DSI, GPU2D, and +2 MB Flash for richer UIs; versus i.MX RT600, it provides hardware-enforced TrustZone isolation, integrated VBAT domain, and lower static power - critical for certified secure, battery-operated devices.

Availability

STM32U595RJT6 is available at Aetrix Electronics and suitable for smart wearable displays, secure industrial HMIs, battery-powered medical sensors, and edge AI gateway nodes requiring stable component supply across long-lifecycle deployments.

Supply support for STM32U595RJT6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive semiconductors.

The STM32U5 series is ST's flagship ultra-low-power MCU line built on the Arm Cortex-M33 core, engineered specifically for secure, graphics-capable, battery-constrained IoT endpoints demanding PSA Certified Level 3 and SESIP compliance.

FAQ

What is the maximum operating frequency and associated performance metric?

The STM32U595RJT6 achieves 160 MHz maximum CPU frequency with 240 DMIPS (Dhrystone 2.1) and 655 CoreMark® (4.09 CoreMark®/MHz), enabled by the ART Accelerator's 32 KB instruction cache eliminating flash wait states. This performance is sustained across the full temperature range (–40 °C to +125 °C) under 3.3 V supply with SMPS active.

How does TrustZone implementation differ from standard Cortex-M33 deployments?

ST implements TrustZone with hardware-enforced partitioning of memories, peripherals, and I/Os via the Global TrustZone Controller (GTZC), plus secure boot rooted in unique device entry and HDP-protected secure services. Unlike generic implementations, it integrates with PWR, RCC, and SYSCFG controllers to enforce security policies during low-power transitions and clock gating - validated per PSA Certified Level 3.

Can the MIPI DSI and LTDC operate simultaneously, and what is the display resolution support?

Yes - the STM32U595RJT6 supports concurrent MIPI DSI (host controller, 2 lanes @ 500 Mbit/s) and LTDC (parallel RGB interface) operation. LTDC drives up to 1024×768@60 Hz; MIPI DSI supports QHD (2560×1440) panels via DSI packet mode. Chrom-GRC dynamically allocates GPU2D resources between both interfaces, enabling hybrid display architectures (e.g., DSI for main screen, LTDC for secondary overlay).

What are the key design considerations for achieving 150 nA Shutdown current?

To reach 150 nA Shutdown, all power domains except VBAT must be fully disabled; external circuitry must not load any pin (especially VDDA, VREF+, or analog inputs); VBAT must supply RTC and backup registers; and all 24 wake-up pins must be externally pulled to valid logic levels (no floating inputs). PCB leakage must be <10 nA, and board-level conformal coating is recommended for humidity-sensitive environments.