STMicroelectronics STM32U595VIT6

Overview

STM32U595VIT6 from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit MCU with TrustZone® and FPU, delivering 240 DMIPS at up to 160 MHz. It integrates 4 MB Flash with ECC, 2.5 MB SRAM (with configurable ECC), LTDC display controller, MIPI® DSI host, Neo-Chrom GPU2D, and hardware security including HASH, TRNG, and secure boot - deployed in battery-powered industrial HMI and medical edge devices requiring certified firmware integrity and sub-μA sleep modes.

For engineers reviewing the STM32U595VIT6 datasheet, STM32U595VIT6 pinout, STM32U595VIT6 application, or STM32U595VIT6 equivalent, key selection criteria include TrustZone-enabled peripheral isolation, LPBAM autonomous peripheral operation in Stop 2 mode, 18.5 µA/MHz Run-mode efficiency at 3.3 V, and dual Octo-SPI interfaces for external memory expansion in resource-constrained embedded designs.

Technical Context

The device implements a dual-cache architecture with 32-Kbyte ICACHE and two 16-Kbyte DCACHEs (DCACHE1 for external memories, DCACHE2 for graphics), enabling zero-wait-state execution and accelerated 2D rendering. Its FlexPowerControl system supports five low-power modes - including Shutdown (150 nA), Standby (195 nA), and Stop 3 with 2.5-MB SRAM retention (8.2 µA) - managed via embedded SMPS and LDO regulators with dynamic voltage scaling.

Security is architected around Arm TrustZone®, with GTZC-enforced memory/peripheral partitioning, securable I/Os, RDP-based life-cycle control, and embedded Root Secure Services (RSS) for Secure Firmware Installation (SFI) and TF-M–based over-the-air updates - all validated against PSA Level 3 and SESIP Level 3 certifications.

Key Specifications

Pinout & Package

LQFP100 (14 × 14 mm, 0.5 mm pitch) package with 100 pins, thermally enhanced for sustained 160 MHz operation in industrial ambient conditions. Pin mapping validated per STMicroelectronics DS13633 Rev 3, Section 4.1–4.2.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.

Compared with STM32U575ZIT6, the STM32U595VIT6 adds full display pipeline (LTDC+DSI+GPU2D) and doubles memory capacity - critical for HMI-rich applications; versus i.MX RT600, it delivers superior sub-µA sleep fidelity, PSA Level 3 certification, and autonomous peripheral offload - essential for battery-critical medical and utility metering.

Availability

STM32U595VIT6 is available at Aetrix Electronics and suitable for industrial HMI, portable medical monitors, smart energy meters, and secure IoT gateways requiring stable component supply across extended product lifecycles.

Supply support for STM32U595VIT6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive semiconductors for industrial, automotive, and consumer markets.

The STM32U5 series is ST's flagship ultra-low-power secure MCU line, engineered for PSA Certified Level 3 and SESIP Level 3 compliance - targeting battery-operated edge devices demanding both cryptographic trust and multi-year runtime.

FAQ

What is the maximum operating temperature range for STM32U595VIT6?

The STM32U595VIT6 is rated for industrial operation from –40 °C to +85 °C, with extended qualification up to +125 °C for select variants. This rating is confirmed in DS13633 Rev 3, Section 5.3.1, and applies to the LQFP100 package under specified voltage and thermal conditions.

Does STM32U595VIT6 support USB Type-C Power Delivery?

Yes - it integrates a dedicated UCPD (USB Type-C Power Delivery) controller compliant with USB PD 3.0 and USB Type-C 1.2 specifications. The UCPD block handles BMC signaling, VCONN switching, and policy engine execution independently of the main CPU, as detailed in Section 3.53 of DS13633 Rev 3.

How does LPBAM reduce system-level power consumption?

LPBAM enables peripherals (e.g., ADC, timers, DMA) to execute preconfigured data chains autonomously in Stop 2 mode without CPU intervention. For example, an ADC can sample, trigger DMA to store results in SRAM, and wake the CPU only upon buffer full - cutting active-mode duty cycle by up to 90% in sensor aggregation use cases.

Can the Neo-Chrom GPU2D render to external SDRAM via Octo-SPI?

Yes - the Neo-Chrom GPU2D supports direct rendering to external memory mapped via either Octo-SPI interface, leveraging DCACHE2 for texture caching. This is enabled through the Chrom-GRC (GFXMMU) unit, which manages address translation and memory protection for graphics buffers outside internal SRAM, as specified in Sections 3.19 and 3.21 of DS13633 Rev 3.