STMicroelectronics STM32U595VIT6Q

Overview

STM32U595VIT6Q from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit microcontroller with TrustZone® security, FPU, and 240 DMIPS performance at up to 160 MHz. It integrates 4 MB Flash (with ECC), 2.5 MB SRAM (ECC-configurable), LTDC display controller, MIPI® DSI host, Neo-Chrom GPU2D, and dual 14-bit ADCs operating at 2.5 Msps - deployed in battery-powered industrial HMIs and secure edge sensor gateways.

For engineers reviewing the STM32U595VIT6Q datasheet, STM32U595VIT6Q pinout, STM32U595VIT6Q application, or STM32U595VIT6Q equivalent, key selection criteria include TrustZone-enabled secure boot, LPBAM autonomous peripheral operation down to Stop 2 mode, 150 nA Shutdown current, 160 MHz clock with ART Accelerator, and dual Octo-SPI interfaces for external memory expansion.

Technical Context

The device implements a dual-cache architecture: 32-Kbyte ICACHE enabling zero-wait-state execution from Flash and external memories, and two independent 16-Kbyte DCACHEs - one for external memories (DCACHE1) and one for graphics (DCACHE2). Its power management includes both LDO and SMPS step-down converters with on-the-fly voltage scaling.

Security is anchored in Arm TrustZone®, augmented by securable I/Os, GTZC-controlled memory/peripheral partitioning, secure firmware installation (SFI), and NIST SP800-90B-compliant TRNG. The low-power design supports LPBAM - enabling DMA-driven peripheral chains (e.g., ADC → GPU → LTDC) without CPU intervention, even in Stop 2 mode.

Key Specifications

Pinout & Package

LQFP100 (14 × 14 mm, 0.5 mm pitch) package with 100 pins. Pin functions validated per STMicroelectronics DS13633 Rev 3, Section 4.2 (Pin description) and Table 12 (Pin mapping for LQFP100).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.

Compared with STM32U575ZIT6, the STM32U595VIT6Q adds MIPI DSI, GPU2D, and 2× Flash/SRAM - essential for rich GUIs. Versus i.MX RT600, it delivers stronger hardware-enforced security and lower static power, at the expense of peak DSP throughput.

Availability

STM32U595VIT6Q is available at Aetrix Electronics and suitable for industrial HMIs, secure smart meters, battery-powered edge gateways, and medical wearables requiring stable component supply across extended product lifecycles.

Supply support for STM32U595VIT6Q includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive chips since 1987.

The STM32U5 series targets ultra-low-power, secure, and graphics-capable embedded applications - engineered for battery longevity, PSA-certifiable security, and human-machine interface responsiveness in industrial and medical edge devices.

FAQ

What is the maximum operating temperature range for STM32U595VIT6Q?

The STM32U595VIT6Q is rated for operation from –40 °C to +125 °C ambient temperature. This extended industrial grade rating is validated per DS13633 Rev 3, Section 5.3.1, and applies across all low-power modes including Stop 2 and VBAT operation. Thermal derating begins above 105 °C for sustained 160 MHz operation.

Does STM32U595VIT6Q support external memory interfaces beyond Octo-SPI?

Yes - it supports SRAM, PSRAM, NOR, NAND, and FRAM via its Flexible Static Memory Controller (FSMC), plus two independent Octo-SPI interfaces and one 16-bit HSPI interface running up to 160 MHz. The FSMC provides asynchronous 8/16-bit bus timing with programmable setup/hold/wait states, validated for Micron MT48LC16M16A2 and Winbond W25N01GV NAND devices.

How does TrustZone implementation differ between STM32U595VIT6Q and earlier STM32L5 MCUs?

The STM32U595VIT6Q enhances TrustZone with Global TrustZone Controller (GTZC) supporting dynamic memory region reconfiguration, secure peripheral gating, and hardware-enforced privilege escalation barriers - unlike STM32L5's fixed GTZC configuration. It also adds Secure Hide-Protection Area (HDP) and Root Secure Services (RSS) for certified SFI, absent in L5-series parts.

Can the Neo-Chrom GPU2D render directly to external SDRAM without CPU involvement?

Yes - Neo-Chrom GPU2D accesses external memory via DCACHE1 and the AHB bus matrix, supporting direct rendering to framebuffer addresses in Octo-SPI PSRAM or FSMC SRAM. ST AN5527 confirms GPU2D command lists can be executed autonomously using LPDMA, with no CPU cycles required for pixel transfer or blending operations.