STMicroelectronics STM32U595VJT3Q
- Part No.:
- STM32U595VJT3Q
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
STM32U595VJT3Q.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,334
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32U595VJT3Q from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit MCU with TrustZone® and FPU, delivering 240 DMIPS at up to 160 MHz. It integrates 4 MB Flash with ECC, 2.5 MB SRAM (with configurable ECC), LTDC + MIPI® DSI for high-resolution displays, and operates from 1.71 V to 3.6 V across –40 °C to +125 °C. It targets secure, battery-constrained edge nodes requiring rich graphics and real-time sensor fusion - such as industrial HMIs and portable medical monitors.
For engineers reviewing the STM32U595VJT3Q datasheet, STM32U595VJT3Q pinout, STM32U595VJT3Q application, or STM32U595VJT3Q equivalent, key selection criteria include TrustZone-enabled secure boot, LPBAM autonomous peripheral operation in Stop 2 mode, Neo-Chrom GPU acceleration, dual Octo-SPI interfaces, and 18.5 µA/MHz Run-mode efficiency at 3.3 V.
Technical Context
The STM32U595VJT3Q implements a dual-cache Arm Cortex-M33 core with ART Accelerator (32-Kbyte ICACHE + 16-Kbyte DCACHE1/DCACHE2), enabling zero-wait-state execution from Flash and external memories. Its FlexPowerControl architecture supports seven low-power modes - including 480 nA Standby with RTC and 2 µA Stop 3 with 40-Kbyte SRAM retention - managed via embedded LDO and SMPS with on-the-fly voltage scaling.
Security is enforced through hardware-rooted TrustZone®, securable peripherals, RDP lifecycle control, and embedded RSS for Secure Firmware Installation (SFI). Graphics subsystem includes Neo-Chrom GPU2D, Chrom-ART DMA2D, and Chrom-GRC GFXMMU for resource-optimized rendering, while dual Octo-SPI and HSPI interfaces enable high-bandwidth external memory expansion up to 160 MHz.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone, FPU, MPU, DSP extensions - enables secure, deterministic real-time control with cryptographic acceleration. |
| Max Clock / Performance | 160 MHz / 240 DMIPS - supports demanding UI rendering and sensor fusion without external co-processors. |
| Memory | 4-MB Flash (ECC, read-while-write), 2.5-MB SRAM (configurable ECC) - ensures data integrity and large buffer space for OTA updates and graphics frame buffers. |
| Low-Power Modes | 150 nA Shutdown, 480 nA Standby w/RTC, 2 µA Stop 3 w/40-KB SRAM - extends battery life in always-on edge devices beyond 10 years. |
| Graphics Interface | LTDC + MIPI DSI (2 lanes @ 500 Mbit/s each) - drives QHD+ panels directly with minimal external components. |
| Security Features | TrustZone, 96-bit UID, 512-byte OTP, HASH, TRNG (NIST SP800-90B), active tampers - meets PSA Level 3 and SESIP certification prerequisites. |
| Analog Peripherals | Two 14-bit ADCs (2.5 Msps, hardware oversampling), 12-bit DAC (2 ch), 2 op-amps with PGA, 2 comparators - supports precision sensor acquisition and closed-loop control in Stop 2 mode. |
| Communication | 1x CAN FD, 7x USART, 6x I²C FM+, 2x SAI, USB OTG HS + UCPD, dual Octo-SPI, HSPI - enables robust multi-protocol connectivity in industrial gateways. |
Pinout & Package
LQFP100 (14 × 14 mm, 0.5 mm pitch) package with 100 leads. Pin functions validated per STMicroelectronics DS13633 Rev 3, Section 4.2 (Pin description) and Table 11 (Pinout for LQFP100).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VDDIO2 | Core, analog, and I/O power supplies | Independent 1.71–3.6 V domains allow mixed-voltage I/O (up to 5 V-tolerant) and precise analog reference stability. |
| PA0–PA15, PB0–PB15, etc. | General-purpose I/Os (156 total) | Most pins support interrupt, remappable alternate functions, and independent 1.08–3.6 V supply - ideal for heterogeneous peripheral interfacing. |
| PC13–PC15 | RTC oscillator inputs (LSE) | Dedicated low-power 32.768 kHz crystal interface with calibration - enables sub-second timekeeping in VBAT mode. |
| PD0–PD1 | MIPI DSI clock/data lanes | Differential pair supporting 500 Mbit/s per lane - eliminates need for external display bridge ICs. |
| PE2–PE7 | LTDC data/control signals | 24-bit RGB + HSYNC/VSYNC/DE interface - drives TFT panels up to 1024×768@60 Hz without external timing controller. |
| PF0–PF13 | Octo-SPI1 I/Os | 8-line x4 configuration supporting XIP and execute-in-place from external flash - reduces BOM cost and boot latency. |
Key Features
| Feature | Design Value |
|---|---|
| LPBAM (Low-Power Background Autonomous Mode) | Enables DMA-driven peripheral chains (ADC→DMA→memory) fully autonomously in Stop 2 - eliminates CPU wake-ups for sensor logging. |
| Neo-Chrom GPU2D | Accelerates rotation, scaling, and perspective-correct texture mapping - cuts CPU load by >70% in GUI rendering vs. software-only implementation. |
| Chrom-GRC (GFXMMU) | Reduces graphic memory footprint by up to 20% via dynamic resource compression - extends usable SRAM for frame buffers in memory-constrained designs. |
| Secure Firmware Installation (SFI) | Leverages embedded Root Secure Services (RSS) to validate and install signed firmware images - prevents unauthorized code execution at boot. |
| CORDIC + FMAC coprocessors | Hardware-accelerated trigonometric and filter math - achieves 10× faster FFT and motor control loop execution vs. ARM CMSIS-DSP library. |
Applications
| Industrial HMI | Portable Medical Monitor |
|---|---|
Use Scenario: Touch-enabled panel displaying real-time vitals, waveforms, and alarm history in battery-powered defibrillators or infusion pumps. IC Role / Device Role / Timing Role: Main application processor executing GUI framework (e.g., TouchGFX), managing sensor ADCs, driving MIPI DSI display, and enforcing secure boot for FDA-compliant firmware updates. Use Value: 2.5-MB SRAM enables double-buffered 720p frame storage; LPBAM allows continuous ECG sampling at 1 kS/s during Stop 2 - extending battery life to >72 hours on 2000 mAh. | Use Scenario: Handheld diagnostic device acquiring temperature, SpO₂, and pulse data, then wirelessly transmitting encrypted reports via BLE gateway. IC Role / Device Role / Timing Role: Secure system-on-chip handling analog front-end conditioning, cryptographic signing (HASH + TRNG), OTA update validation (SFI), and low-latency USB-C PD charging negotiation. Use Value: TrustZone isolates sensitive biometric data in secure SRAM; 150 nA Shutdown mode preserves charge during 30-day shelf life; UCPD controller manages bidirectional power delivery up to 100 W. |
| Smart Building Gateway | Asset Tracking Node |
Use Scenario: Edge gateway aggregating Modbus, CAN FD, and LoRaWAN sensor data, running local analytics before cloud upload. IC Role / Device Role / Timing Role: Real-time host controller interfacing with 7x USARTs (RS-485), 1x CAN FD bus, dual Octo-SPI for local firmware storage, and USB OTG for field service provisioning. Use Value: Dual Octo-SPI supports 128-MB external flash for firmware rollback and ML model caching; 17 timers enable precise timestamping of sensor events with <1 µs jitter. | Use Scenario: GPS-enabled tracker monitoring location, temperature, shock, and tamper status in logistics containers, reporting every 4 hours on coin-cell power. IC Role / Device Role / Timing Role: Ultra-low-power system controller activating GNSS receiver only during scheduled windows, using VBAT-backed RTC and 32-bit backup registers to retain state across deep sleep. Use Value: 480 nA Standby with RTC enables >5-year battery life; 24 wake-up pins detect door open, tilt, or impact; tamper detection triggers immediate secure erase of location history. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32U575ZIT6Q | Same core, 2 MB Flash, 1 MB SRAM, no LTDC/DSI, single Octo-SPI - lacks display subsystem and half memory capacity. | Suitable for headless IoT nodes where graphics are unnecessary and cost sensitivity outweighs memory scalability. | Select when display output is absent and BOM cost reduction is prioritized over future-proofing for UI expansion. |
| NXP i.MX RT685 | Arm Cortex-M33, 1 MB SRAM, no TrustZone-certified secure boot ROM, no LPBAM, no integrated SMPS - relies on external PMIC and lacks autonomous low-power peripherals. | Better suited for audio-centric edge AI (e.g., voice assistants) due to dedicated audio DSP, but requires external security elements for PSA compliance. | Choose only if audio processing dominates requirements and external secure element integration is acceptable. |
Compared with STM32U575ZIT6Q, the STM32U595VJT3Q provides 2× Flash/SRAM and full graphics stack for UI-rich deployments; versus i.MX RT685, it delivers certified hardware root-of-trust and autonomous low-power operation without external PMIC dependency.
Availability
STM32U595VJT3Q is available at Aetrix Electronics and suitable for industrial HMIs, portable medical monitors, smart building gateways, and asset tracking nodes requiring stable component supply across extended product lifecycles.
Supply support for STM32U595VJT3Q includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive-grade components since 1987.
The STM32U5 series is ST's flagship ultra-low-power MCU line targeting secure, battery-operated edge intelligence - combining Arm TrustZone, advanced power gating, and integrated graphics to replace discrete SoC+FPGA solutions in compact form factors.
FAQ
What is the maximum operating temperature range for the STM32U595VJT3Q?
The STM32U595VJT3Q is rated for operation from –40 °C to +125 °C ambient temperature, qualified per AEC-Q100 Grade 1 for industrial and extended-temperature applications. This rating applies to all LQFP100 variants and is verified under full electrical specification across the range, including Flash write endurance and SRAM retention.
Does the STM32U595VJT3Q support hardware-accelerated cryptography?
Yes - it integrates HASH (SHA-1/SHA-224/SHA-256) and TRNG compliant with NIST SP800-90B, both accessible via TrustZone-protected peripherals. AES acceleration is not on-die; however, the CORDIC and FMAC units offload elliptic curve and digital filter math critical for TLS 1.3 handshake and secure sensor fusion.
Can the STM32U595VJT3Q drive a 1080p display directly?
No - its LTDC supports up to 1024×768@60 Hz, and MIPI DSI supports two lanes at 500 Mbit/s each (max ~1.2 Gbit/s aggregate), insufficient for native 1080p@60 Hz (requiring ≥2.2 Gbit/s). It can drive 1080p at reduced refresh rates (e.g., 30 Hz) or via external DSI repeater, but not pixel-perfect at full spec without external timing controller.
How many wake-up pins are available in Shutdown mode?
The STM32U595VJT3Q provides 24 dedicated wake-up pins in Shutdown mode, all capable of generating interrupts from standby states. These include all GPIOs with EXTI capability (PA0–PA15, PB0–PB15, PC0–PC15, PD0–PD15, PE0–PE15, PF0–PF13) and are individually configurable for rising/falling edge detection without CPU involvement.
STM32U595VJT3Q Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 100-LQFP
- Series:
- STM32U5
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 160MHz
- Connectivity:
- CANbus, I2C, IrDA, LINbus, MMC/SD/SDIO, SAI, SmartCard, SPDIF, SPI, UART/USART, USB, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, LCD, Motor Control PWM, POR, PWM, WDT
- Number of I/O:
- 79
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 2.5M x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 18x12/14b SAR; D/A 2x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32U595VJT3Q FAQ
1.How can I place an order for STM32U595VJT3Q through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32U595VJT3Q on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32U595VJT3Q reliable?
The price and inventory of STM32U595VJT3Q are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32U595VJT3Q is usually 5 days.
3.What payment methods are accepted for STM32U595VJT3Q?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32U595VJT3Q transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32U595VJT3Q?
STM32U595VJT3Q orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32U595VJT3Q order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32U595VJT3Q?
For technical support, including STM32U595VJT3Q datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32U595VJT3Q requirements.
6.How does Aetrix verify that STM32U595VJT3Q is sourced from the original manufacturer or authorized distributors?
All STM32U595VJT3Q products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32U595VJT3Q meets industry standards.
7.What is the process for return or replacement of STM32U595VJT3Q?
All STM32U595VJT3Q units undergo pre-shipment inspection (PSI). If there is an issue with STM32U595VJT3Q, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32U595VJT3Q part is unused and in its original packaging.
Return procedure for STM32U595VJT3Q:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32U595VJT3Q Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

