STMicroelectronics STM32U595VJT3QTR
- Part No.:
- STM32U595VJT3QTR
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
STM32U595VJT3QTR.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:2,205
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32U595VJT3QTR from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit MCU with TrustZone®, FPU, and FlexPowerControl - delivering 240 DMIPS at up to 160 MHz, 4 MB Flash with ECC, and 2.5 MB SRAM. It integrates MIPI® DSI host controller (dual 500 Mbit/s lanes), LTDC, Neo-Chrom GPU2D, and dual 14-bit ADCs (2.5 Msps), targeting secure, graphics-rich IoT edge nodes and battery-powered HMI displays.
For engineers reviewing the STM32U595VJT3QTR datasheet, STM32U595VJT3QTR pinout, STM32U595VJT3QTR application, or STM32U595VJT3QTR equivalent, key selection criteria include TrustZone-enabled secure boot, LPBAM autonomous peripheral operation in Stop 2 mode, 150 nA Shutdown current, 160 MHz clock with ART Accelerator, and dual DSI + LTDC support for high-resolution embedded displays.
Technical Context
This MCU implements a dual-bank Flash architecture with read-while-write capability and hardware ECC, enabling secure over-the-air firmware updates without runtime interruption. Its TrustZone security subsystem enforces strict isolation between secure and non-secure worlds, managing access to memories, peripherals (including GTZC-controlled DMA2D and OCTOSPI), and debug interfaces via RDP and HDP protection.
The power architecture combines embedded LDO and SMPS step-down converter with dynamic voltage scaling and on-the-fly switching, supporting five low-power modes - including Stop 2 with autonomous ADC/DAC operation and LPBAM-driven DMA transfers - all validated down to -40°C to +125°C operating temperature.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone, FPU, MPU, and DSP extensions - enables secure real-time control with cryptographic acceleration and memory partitioning. |
| Max Clock / Performance | 160 MHz / 240 DMIPS - achieved via 32-Kbyte ICACHE and ART Accelerator, enabling zero-wait-state execution from Flash. |
| Memory | 4-MB Flash (ECC, dual-bank RWW), 2.5-MB SRAM (with configurable ECC) - supports robust firmware resilience and large buffer handling for graphics/audio. |
| Low-Power Modes | 150 nA Shutdown, 195 nA Standby, 4.65 µA Stop 2 (40 KB SRAM retained) - enables multi-year battery life in sensor-hub and wearable applications. |
| Graphics Interface | MIPI DSI host (2 lanes @ 500 Mbit/s each) + LTDC + Neo-Chrom GPU2D + Chrom-ART DMA2D - drives QXGA (2048×1536) displays with hardware-accelerated rotation/scaling. |
| Analog Peripherals | Dual 14-bit ADCs (2.5 Msps, hardware oversampling), 12-bit DAC (2 ch), 2 op-amps with PGA, 2 ultra-low-power comparators - supports precision sensor fusion and analog signal conditioning. |
| Security Features | TrustZone, Secure Boot with unique entry, 512-byte OTP, HASH accelerator, NIST SP800-90B TRNG, active tampers - meets PSA Certified Level 3 and SESIP requirements. |
| Communication | 1x CAN FD, 7x USART, 6x I²C FM+, 3x SPI + 2x OCTOSPI + 1x HSPI, 2x SDMMC, USB OTG HS + UCPD - enables mixed wired/wireless connectivity in industrial gateways. |
Pinout & Package
LQFP100 (14 × 14 mm, 0.5 mm pitch) package with 100 pins. Pin functions include VDD/VSS power rails, 32-bit address/data bus for FSMC, dual DSI differential pairs (CLKP/N, DAT0P/N–DAT1P/N), LTDC RGB interface (24-bit), and dedicated TrustZone-secured debug (SWCLK/SWDIO) and reset (NRST) terminals.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PA0–PA15, PB0–PB15, etc. | General-purpose I/O | Up to 156 fast GPIOs; most 5V-tolerant, 14 with independent 1.08–3.6 V supply - supports mixed-voltage interfacing and flexible peripheral mapping. |
| PD0–PD15 | FSMC Data/Address Bus | 16-bit parallel interface for NOR/PSRAM/FRAM - enables external display frame buffer or code execution off-chip. |
| PE2–PE12 | LTDC RGB Interface | 24-bit RGB + HSYNC/VSYNC/DE - directly drives TFT panels without external timing controller. |
| PF10–PF15, PG0–PG15 | MIPI DSI Lane Signals | Dual differential lanes (CLKP/N, DAT0P/N, DAT1P/N) - supports high-speed, low-noise display streaming with ESD-protected routing. |
| PC13–PC15 | RTC/LSE Support | 32.768 kHz crystal input and RTC backup domain - maintains calendar/time across full power cycles and VBAT operation. |
Key Features
| Feature | Design Value |
|---|---|
| LPBAM Autonomous Mode | Enables DMA-driven peripheral chains (ADC→DMA→memory) without CPU wake-up - reduces active time by >90% in sensor logging. |
| Neo-Chrom GPU2D | Hardware-accelerated 2D graphics: arbitrary-angle rotation, perspective-correct texture mapping, alpha blending - cuts CPU load by ~70% in GUI rendering. |
| Chrom-GRC (GFXMMU) | Dynamic graphic resource compression - reduces framebuffer memory footprint by up to 20%, easing SRAM constraints in high-res UIs. |
| CORDIC + FMAC Coprocessors | Offloads trigonometric (sin/cos/tan) and FIR/IIR filter computations - accelerates motor control and audio preprocessing with deterministic latency. |
| Secure Firmware Installation (SFI) | Embedded Root Secure Services (RSS) validate and install signed firmware images - eliminates need for external secure element in OTA update paths. |
Applications
| Smart Wearable Display | Industrial HMI Terminal |
|---|---|
Use Scenario: Battery-powered smartwatch with always-on color display and biometric sensing. IC Role / Device Role / Timing Role: Main application processor executing RTOS, driving MIPI DSI display, sampling PPG/ECG sensors via autonomous ADC in Stop 2 mode. Use Value: 195 nA Standby current extends battery life beyond 14 days; LPBAM enables continuous heart-rate monitoring with <1 µA average current. | Use Scenario: Panel-mounted human-machine interface for factory automation with touch, graphics, and fieldbus connectivity. IC Role / Device Role / Timing Role: Graphics controller running LVGL GUI stack, interfacing to CAN FD PLC network and SD card for recipe storage. Use Value: LTDC + Neo-Chrom GPU2D renders 1024×600 UI at 60 fps with <5% CPU utilization; TrustZone isolates HMI firmware from fieldbus stack. |
| Secure IoT Gateway | Medical Sensor Hub |
Use Scenario: Edge gateway aggregating BLE/Wi-Fi sensor data, performing local analytics, and forwarding to cloud via Ethernet/USB. IC Role / Device Role / Timing Role: Secure application host with TF-M-based PSA Level 3 attestation, USB OTG HS for diagnostics, and dual OCTOSPI for encrypted firmware+data storage. Use Value: HASH + TRNG + OTP enable TLS 1.3 handshake acceleration and device identity binding; 4 MB Flash supports dual-image secure boot rollback. | Use Scenario: Portable patient monitor collecting ECG, SpO₂, and temperature with local alarm logic and Bluetooth LE telemetry. IC Role / Device Role / Timing Role: Low-power analog front-end controller with autonomous ADC/DAC, op-amp PGA gain staging, and tamper-detect RTC backup. Use Value: 12-bit DAC + 2 op-amps generate calibrated reference signals; VBAT mode retains 2 KB backup SRAM and RTC during main power loss - ensures no vital data loss. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32U575ZIT6Q | Same core, 2 MB Flash, 1 MB SRAM, no MIPI DSI or LTDC - lacks display interfaces and GPU2D. | Suitable for secure sensor hubs or crypto modules without graphics. | Select when display capability is unnecessary and cost/BOM size optimization is critical. |
| RA6M5GFEK0 | Arm Cortex-M33, 1 MB Flash, 512 KB SRAM, no TrustZone hardware partitioning - relies on software-enforced security. | Targeted at industrial control with CAN FD and Ethernet, but lower security assurance. | Choose only if PSA Level 2 suffices and external secure element is acceptable for key management. |
Compared with STM32U575ZIT6Q, this part adds MIPI DSI/LTDC and doubles Flash/SRAM for rich UIs; versus RA6M5GFEK0, it delivers hardware-enforced TrustZone isolation and higher memory bandwidth - essential for certified medical or payment-grade devices.
Availability
STM32U595VJT3QTR is available at Aetrix Electronics and suitable for battery-powered wearables, industrial HMIs, secure IoT gateways, and portable medical devices requiring stable component supply across long product lifecycles.
Supply support for STM32U595VJT3QTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive semiconductors.
The STM32U5 series targets ultra-low-power, secure, and graphics-capable embedded applications - engineered specifically for next-generation IoT endpoints where energy efficiency, safety certification, and rich user interfaces converge.
FAQ
What is the maximum operating temperature rating for STM32U595VJT3QTR?
The STM32U595VJT3QTR is qualified for operation from -40°C to +125°C ambient temperature, verified per JEDEC JESD47 stress testing. This extended range supports deployment in under-hood automotive modules, industrial motor drives, and outdoor edge gateways without thermal derating.
Does STM32U595VJT3QTR support hardware-accelerated cryptography?
Yes - it integrates a dedicated HASH hardware accelerator supporting SHA-1, SHA-224, and SHA-256, plus a NIST SP800-90B compliant True Random Number Generator (TRNG). These blocks operate independently of the CPU and are accessible from both secure and non-secure worlds under TrustZone policy control.
Can the MIPI DSI interface drive dual displays simultaneously?
No - the STM32U595VJT3QTR features a single MIPI DSI host controller with two data lanes and one clock lane, supporting only one DSI display port. Dual-display output requires external bridge ICs or time-multiplexed panel switching, not native hardware support.
What debug interfaces are available and are they TrustZone-protected?
It supports Serial Wire Debug (SWD) and JTAG via dedicated SWCLK/SWDIO/NRST pins. All debug access is governed by TrustZone's Global TrustZone Controller (GTZC); debug privilege is enforced through RDP level and password-protected secure debug enable - preventing unauthorized access even in production units.
STM32U595VJT3QTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 100-LQFP
- Series:
- STM32U5
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 160MHz
- Connectivity:
- CANbus, I2C, IrDA, LINbus, MMC/SD/SDIO, SAI, SmartCard, SPDIF, SPI, UART/USART, USB, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, LCD, Motor Control PWM, POR, PWM, WDT
- Number of I/O:
- 79
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 2.5M x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 18x12/14b SAR; D/A 2x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32U595VJT3QTR FAQ
1.How can I place an order for STM32U595VJT3QTR through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32U595VJT3QTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32U595VJT3QTR reliable?
The price and inventory of STM32U595VJT3QTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32U595VJT3QTR is usually 5 days.
3.What payment methods are accepted for STM32U595VJT3QTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32U595VJT3QTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32U595VJT3QTR?
STM32U595VJT3QTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32U595VJT3QTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32U595VJT3QTR?
For technical support, including STM32U595VJT3QTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32U595VJT3QTR requirements.
6.How does Aetrix verify that STM32U595VJT3QTR is sourced from the original manufacturer or authorized distributors?
All STM32U595VJT3QTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32U595VJT3QTR meets industry standards.
7.What is the process for return or replacement of STM32U595VJT3QTR?
All STM32U595VJT3QTR units undergo pre-shipment inspection (PSI). If there is an issue with STM32U595VJT3QTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32U595VJT3QTR part is unused and in its original packaging.
Return procedure for STM32U595VJT3QTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32U595VJT3QTR Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

