STMicroelectronics STM32U595VJT6Q
- Part No.:
- STM32U595VJT6Q
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
STM32U595VJT6Q.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:2,414
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Product details
Overview
STM32U595VJT6Q from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit MCU with TrustZone® and FPU, delivering 240 DMIPS at up to 160 MHz. It integrates 4 MB Flash with ECC, 2.5 MB SRAM (with configurable ECC), LTDC + MIPI® DSI for high-resolution display control, and operates from 1.71 V to 3.6 V across –40 °C to +125 °C. It targets secure, battery-constrained edge nodes requiring graphics acceleration and cryptographic integrity - e.g., industrial HMI panels with touch-enabled GUIs.
For engineers reviewing the STM32U595VJT6Q datasheet, STM32U595VJT6Q pinout, STM32U595VJT6Q application, or STM32U595VJT6Q equivalent, key selection criteria include TrustZone-enforced memory partitioning, LPBAM autonomous peripheral operation in Stop 2 mode, Neo-Chrom GPU2D support for rotation/scaling, dual Octo-SPI interfaces for external code/data, and 156 GPIOs with 5 V tolerance and independent supply capability down to 1.08 V.
Technical Context
This MCU implements a dual-cache architecture with 32 KB ICACHE and two 16 KB DCACHEs (DCACHE1 for external memories, DCACHE2 for graphics), enabling zero-wait-state execution and efficient GPU/DSI data flow. Its FlexPowerControl system supports seven low-power modes - including 195 nA Standby and 480 nA Standby with RTC - managed via embedded SMPS and LDO regulators with on-the-fly voltage scaling.
The security stack combines Arm TrustZone with hardware root of trust: securable I/Os, RDP-protected debug, secure hide-protection area (HDP), and embedded Root Secure Services (RSS) for Secure Firmware Installation (SFI) and TF-M–based firmware upgrades. Analog subsystem includes two 14-bit ADCs (2.5 Msps), one 12-bit ADC autonomous in Stop 2, dual DACs, two op-amps with PGA, and two ultra-low-power comparators - all with independent supply domains.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone, FPU, MPU, DSP extensions - enables secure real-time control with hardware-isolated secure/non-secure worlds. |
| Max Clock / Performance | 160 MHz / 240 DMIPS - supports complex UI rendering and sensor fusion without external co-processors. |
| Memory | 4 MB Flash (ECC, read-while-write), 2.5 MB SRAM (configurable ECC allocation) - sufficient for OTA-upgradable secure firmware + graphics frame buffers. |
| Low-Power Modes | 195 nA Standby (24 wake-up pins), 480 nA Standby+RTC, 2 μA Stop 3 (40 KB SRAM retained) - extends battery life in always-on industrial sensors. |
| Graphics Interface | LTDC + MIPI DSI host (2 lanes @ 500 Mbit/s each) + Neo-Chrom GPU2D + Chrom-ART DMA2D - drives 1080p displays with hardware-accelerated rotation and transparency. |
| Security | TrustZone + HDP + RSS + HASH + TRNG (NIST SP800-90B compliant) + 96-bit UID + 512-byte OTP - meets PSA Level 3 and SESIP certification prerequisites. |
| Analog Peripherals | 2× 14-bit ADC (2.5 Msps), 1× 12-bit ADC (autonomous in Stop 2), 2× DAC, 2× op-amp w/PGA, 2× comparator - supports simultaneous multi-sensor acquisition with minimal CPU load. |
| Communication | 1× CAN FD, 1× USB OTG HS, 1× UCPD, 7× USART, 6× I²C, 3× SPI, 2× SAI, 2× SDMMC - enables robust connectivity in mixed-protocol industrial gateways. |
Pinout & Package
LQFP100 (14 × 14 mm, 0.5 mm pitch) package with 100 leads. Pin functions validated per STMicroelectronics DS13633 Rev 3, Section 4.2 (Pin description) and Table 12 (Pin mapping for LQFP100).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VDDIO2 | Core, analog, and I/O power supplies | Independent domains allow mixed-voltage I/O (down to 1.08 V) while maintaining 3.3 V core operation and precision analog performance. |
| PA0–PA15, PB0–PB15, etc. | General-purpose I/Os (156 total) | Most are 5 V-tolerant; up to 14 support independent VDDIO2 supply - critical for interfacing legacy peripherals or level-shifted sensors. |
| PC10–PC12, PD3–PD7 | MIPI DSI lane and clock outputs | Dedicated high-speed differential pairs supporting 500 Mbit/s per lane - directly drive DSI displays without external PHY. |
| PE0–PE11 | LTDC RGB interface + sync signals | 16-bit parallel RGB output with HSYNC/VSYNC/DE timing - enables direct connection to TFT panels without external controller. |
| PF0–PF13 | Octo-SPI1 and Octo-SPI2 interfaces | Two independent octal SPI controllers supporting XIP from NOR/PSRAM/FRAM - eliminates boot ROM dependency and reduces BOM cost. |
| NRST | Active-low reset input | Asynchronous reset with internal pull-up; compatible with external supervisor ICs meeting IEC 61000-4-2 ESD immunity requirements. |
Key Features
| Feature | Design Value |
|---|---|
| LPBAM (Low-Power Background Autonomous Mode) | Enables DMA-driven peripheral chains (e.g., ADC → memory → crypto) without CPU wake-up - reduces active time by >90 % in sensor logging applications. |
| Neo-Chrom GPU2D | Hardware-accelerated 2D graphics: arbitrary-angle rotation, perspective-correct texture mapping, and alpha blending - cuts CPU load by ~70 % vs. software rendering in GUI frameworks. |
| Chrom-GRC (GFXMMU) | Dynamic graphics resource compression reducing framebuffer memory footprint by up to 20 % - extends usable SRAM for application logic in memory-constrained HMIs. |
| Secure Firmware Installation (SFI) | Uses embedded Root Secure Services (RSS) to validate and install signed firmware images - eliminates need for external secure element in certified IoT endpoints. |
| VBAT domain retention | RTC + 32 × 32-bit backup registers + 2 KB backup SRAM powered independently - preserves timekeeping and state during main power loss in smart meters. |
| CORDIC + FMAC coprocessors | Hardware acceleration for trigonometric (sin/cos/tan) and FIR/IIR filter computations - achieves 10× speedup over Cortex-M33 integer arithmetic in motor control loops. |
Applications
| Industrial HMI Panel | Smart Energy Meter |
|---|---|
Use Scenario: Touch-enabled graphical interface for factory floor equipment monitoring with real-time data visualization and alarm management. IC Role / Device Role / Timing Role: Primary application processor managing LTDC/DSI display pipeline, running FreeRTOS with TrustZone-secured communication stacks, and executing CORDIC-based sensor calibration. Use Value: GPU2D + DMA2D offloads GUI rendering from CPU, enabling 60 fps animation at <15 % CPU utilization while maintaining deterministic response to touch interrupts. |
Use Scenario: Revenue-grade electricity meter with tamper detection, time-of-use billing, and secure remote firmware updates over PLC or NB-IoT. IC Role / Device Role / Timing Role: Secure system-on-chip handling metrology ADC sampling, RTC calendar, cryptographic signing of consumption logs, and TLS-secured OTA updates via UCPD/USB. Use Value: TrustZone isolation prevents malicious firmware from accessing metrology registers or tampering with RTC calibration - satisfying IEC 62056 and UL 2900-1 requirements. |
| Wearable Medical Sensor Hub | Secure Edge Gateway |
Use Scenario: Battery-powered wearable aggregating ECG, SpO₂, and motion data with local anomaly detection before cloud upload. IC Role / Device Role / Timing Role: Ultra-low-power host managing autonomous ADC/DAC chains in Stop 2 mode, running lightweight ML inference on FMAC-accelerated filters, and initiating BLE via UART. Use Value: 480 nA Standby+RTC and LPBAM-driven sensor acquisition extend battery life to >12 months on a 300 mAh coin cell without compromising data fidelity. |
Use Scenario: Industrial gateway connecting Modbus RTU field devices to MQTT cloud platforms with encrypted tunneling and firmware rollback protection. IC Role / Device Role / Timing Role: Secure protocol translator using CAN FD for fieldbus, USB OTG for diagnostics, and TLS 1.3 via HASH+TRNG for secure TLS handshake. Use Value: Hardware-accelerated SecureMark™-TLS (120,000 score) enables full TLS 1.3 handshakes in <80 ms - eliminating latency bottlenecks in time-critical SCADA polling cycles. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32U575ZIT6 | Same core, 2 MB Flash, 1 MB SRAM, no LTDC/DSI, no Neo-Chrom GPU, single Octo-SPI | Suitable for secure sensor nodes or BLE gateways without display requirements | Select when graphics capability and >2 MB Flash are unnecessary - reduces cost and PCB area. |
| NXP i.MX RT600 | Arm Cortex-M33 + DSP, 1 MB SRAM, no TrustZone-enforced flash ECC, no LPBAM, no dedicated DSI/LTDC | Better suited for audio DSP workloads; lacks integrated display engine and sub-μA low-power modes | Prefer for voice-enabled edge devices needing high MIPS/MHz but not industrial HMI or extreme energy constraints. |
Compared with STM32U575ZIT6, the STM32U595VJT6Q adds display subsystems and doubles memory capacity for rich GUIs; versus i.MX RT600, it delivers superior ultra-low-power autonomy and hardware-enforced security - making it optimal for certified, battery-operated HMIs.
Availability
STM32U595VJT6Q is available at Aetrix Electronics and suitable for industrial HMI panels, smart energy meters, wearable medical sensor hubs, and secure edge gateways requiring stable component supply across extended product lifecycles.
Supply support for STM32U595VJT6Q includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive semiconductors since 1987.
The STM32U5 series is ST's flagship ultra-low-power secure MCU line, engineered for PSA Certified Level 3 and SESIP-certified applications in industrial, healthcare, and smart infrastructure - emphasizing energy efficiency, hardware-rooted security, and integrated graphics.
FAQ
What is the maximum operating temperature rating for STM32U595VJT6Q?
The device is qualified for operation from –40 °C to +125 °C ambient temperature, verified per JEDEC JESD22-A104 and JESD22-A108 reliability standards. This extended range supports deployment in unventilated industrial enclosures and automotive under-hood environments where thermal management is constrained.
Does STM32U595VJT6Q support hardware-accelerated TLS 1.3?
Yes - the integrated HASH accelerator and NIST SP800-90B–compliant TRNG enable full TLS 1.3 handshake acceleration, achieving a SecureMark™-TLS score of 120,000. This allows sub-80 ms handshakes with ECDSA P-256 keys, verified in ST's AN5512 application note using Mbed TLS.
How many wake-up pins are available in Standby mode?
24 dedicated wake-up pins are supported in Standby mode, confirmed in DS13633 Rev 3 Section 3.9.3. These include all GPIOs configured as EXTI lines, plus dedicated VBAT and RTC alarms - enabling flexible event-driven wake-up from 195 nA quiescent current.
Is the Neo-Chrom GPU2D capable of rendering vector graphics?
No - Neo-Chrom GPU2D accelerates raster-based 2D operations only: bitmap rotation, scaling, alpha blending, and perspective-correct texture mapping. Vector graphics (e.g., SVG) require CPU-side rasterization; GPU2D does not execute vector instruction sets or path rendering engines.
STM32U595VJT6Q Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 100-LQFP
- Series:
- STM32U5
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 160MHz
- Connectivity:
- CANbus, I2C, IrDA, LINbus, MMC/SD/SDIO, SAI, SmartCard, SPDIF, SPI, UART/USART, USB, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, LCD, Motor Control PWM, POR, PWM, WDT
- Number of I/O:
- 79
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 2.5M x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 18x12/14b SAR; D/A 2x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32U595VJT6Q FAQ
1.How can I place an order for STM32U595VJT6Q through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32U595VJT6Q on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32U595VJT6Q reliable?
The price and inventory of STM32U595VJT6Q are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32U595VJT6Q is usually 5 days.
3.What payment methods are accepted for STM32U595VJT6Q?
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4.How is shipping managed for STM32U595VJT6Q?
STM32U595VJT6Q orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32U595VJT6Q order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32U595VJT6Q?
For technical support, including STM32U595VJT6Q datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32U595VJT6Q requirements.
6.How does Aetrix verify that STM32U595VJT6Q is sourced from the original manufacturer or authorized distributors?
All STM32U595VJT6Q products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32U595VJT6Q meets industry standards.
7.What is the process for return or replacement of STM32U595VJT6Q?
All STM32U595VJT6Q units undergo pre-shipment inspection (PSI). If there is an issue with STM32U595VJT6Q, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32U595VJT6Q part is unused and in its original packaging.
Return procedure for STM32U595VJT6Q:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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