STMicroelectronics STM32U595ZIT6Q
- Part No.:
- STM32U595ZIT6Q
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
STM32U595ZIT6Q.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 144LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:3,774
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Product details
Overview
STM32U595ZIT6Q from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit MCU with TrustZone® and FPU, delivering 240 DMIPS at up to 160 MHz. It integrates 4 MB Flash with ECC, 2.5 MB SRAM (with configurable ECC), LTDC, MIPI® DSI host controller, Neo-Chrom GPU, and hardware security features including HASH, TRNG, and secure firmware upgrade support via TF-M. It targets battery-powered industrial HMI and secure edge nodes requiring high graphics throughput and sub-µA standby operation.
For engineers reviewing the STM32U595ZIT6Q datasheet, STM32U595ZIT6Q pinout, STM32U595ZIT6Q application, or STM32U595ZIT6Q equivalent, key selection criteria include TrustZone-enabled secure boot, LPBAM autonomous peripheral operation in Stop 2 mode, 17.5 µA Stop 3 mode with full 2.5-MB SRAM retention, MIPI DSI lane timing compliance (500 Mbit/s), and dual 14-bit ADCs with hardware oversampling for sensor fusion.
Technical Context
The STM32U595ZIT6Q implements a dual-bank Flash architecture supporting read-while-write and 100-kcycle endurance on 512 KB, with SRAM partitioning enabling ECC-on/off configuration across 2.5 MB. Its power architecture combines embedded LDO and SMPS with dynamic voltage scaling and FlexPowerControl, enabling 150 nA Shutdown mode and 480 nA Standby with RTC.
Security is implemented via Arm TrustZone®, securable peripherals, Root of Trust with unique boot entry and HDP, and Secure Firmware Installation (SFI) using embedded RSS. Graphics acceleration leverages Neo-Chrom GPU (GPU2D), Chrom-ART Accelerator (DMA2D), and Chrom-GRC (GFXMMU) for 20% resource optimization in TFT-LCD and DSI-based displays.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone, FPU, MPU, DSP - enables secure real-time control with cryptographic isolation and floating-point math for motor/sensor algorithms. |
| Max Clock / Performance | 160 MHz / 240 DMIPS - supports deterministic execution of complex UI rendering and protocol stacks without external clock sources. |
| Memory | 4 MB Flash (ECC, RWW), 2.5 MB SRAM (configurable ECC) - allows large OTA firmware images and dual-bank secure updates with zero downtime. |
| Low-Power Modes | 150 nA Shutdown, 480 nA Standby w/RTC, 17.5 µA Stop 3 w/2.5-MB SRAM - enables multi-year battery life in always-on sensing and display applications. |
| Graphics Interface | MIPI DSI host (2 lanes @ 500 Mbit/s), LTDC, Neo-Chrom GPU - drives high-resolution color displays (e.g., 800×480 RGB) with hardware-accelerated rotation and texture mapping. |
| Analog Peripherals | 2×14-bit ADC @ 2.5 Msps (oversampling), 12-bit DAC ×2, 2 OPAMP, 2 COMP - supports simultaneous high-precision sensor acquisition and analog feedback control in Stop 2 mode. |
| Security Features | TrustZone, 96-bit UID, 512-byte OTP, HASH, NIST SP800-90B TRNG, SFI/TF-M - meets PSA Level 3 and SESIP certification requirements for secure IoT endpoints. |
Pinout & Package
LQFP144 (20 × 20 mm, 0.5 mm pitch) package with 156 fast I/Os - 5V-tolerant on most pins, 14 I/Os support independent 1.08–3.6 V supply for mixed-voltage interfacing.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VDDIO2 | Core, analog, and I/O power supplies | Independent domains enable low-noise ADC operation and flexible voltage rail sequencing during wake-up. |
| VBAT | Backup power supply | Retains RTC, 32×32-bit backup registers, and 2-KB backup SRAM during main power loss. |
| PA0–PA15, PB0–PB15, etc. | General-purpose I/Os | 156 total I/Os with interrupt capability; up to 14 support 1.08 V logic for ultra-low-power sensor interfaces. |
| PD0–PD15 | LTDC data/control signals | Direct parallel RGB interface to TFT panels; supports 24-bit color depth and pixel clocks up to 80 MHz. |
| PE2–PE12 | MIPI DSI lane and control | Dedicated DSI PHY pins for two high-speed lanes (500 Mbit/s each) and escape-mode signaling. |
| PF0–PF15 | OCTOSPI/HSPI memory interface | Supports external PSRAM/NOR/FRAM up to 160 MHz; enables code execution and frame buffer offload. |
Key Features
| Feature | Design Value |
|---|---|
| LPBAM (Low-Power Background Autonomous Mode) | Enables DMA-driven peripheral chains (ADC→DMA→SRAM→COMP) without CPU wake-up - reduces active time by >90% in sensor logging. |
| Neo-Chrom GPU + Chrom-ART Accelerator | Hardware-accelerated 2D graphics (rotation, scaling, alpha blending) - eliminates CPU load for smooth GUI animation at 60 fps on 800×480 displays. |
| Secure Boot + TF-M Integration | Root of trust with immutable boot entry and HDP-protected keys - ensures only signed, verified firmware executes post-reset. |
| Dual 14-bit ADC with Oversampling | 2.5 Msps sampling with 16× hardware oversampling yields effective 16-bit resolution at 156 kSPS - suitable for precision current/voltage monitoring. |
| SMPS + LDO Dual Regulator | On-the-fly switching between SMPS (high efficiency) and LDO (low noise) - optimizes power vs. analog performance dynamically per system state. |
Applications
| Industrial HMI Panel | Secure Wireless Sensor Node |
|---|---|
Use Scenario: Touch-enabled factory floor display with real-time machine status, alarm history, and parameter adjustment. IC Role / Device Role / Timing Role: Main application processor managing LTDC-driven TFT, MIPI DSI touch controller interface, and secure OTA update engine. Use Value: Neo-Chrom GPU renders animated gauges and trend charts without CPU load; TrustZone isolates UI runtime from secure firmware update partition. | Use Scenario: Battery-powered environmental monitor with temperature/humidity/pressure sensors, BLE/Wi-Fi coexistence, and tamper detection. IC Role / Device Role / Timing Role: System-on-chip handling sensor acquisition (dual ADC), crypto acceleration (HASH/TRNG), and low-power wireless stack scheduling. Use Value: 150 nA Shutdown mode extends 10-year battery life; LPBAM autonomously logs sensor data to SRAM while CPU remains off. |
| Medical Wearable Display | Smart Energy Meter UI |
Use Scenario: Compact wearable with OLED or color LCD showing vital signs, battery level, and Bluetooth pairing status. IC Role / Device Role / Timing Role: Graphics-optimized MCU driving MIPI DSI display, managing capacitive touch, and executing certified medical firmware. Use Value: 480 nA Standby with RTC maintains timekeeping and wake-on-touch; Chrom-GRC reduces GPU memory bandwidth by 20%, lowering display subsystem power. | Use Scenario: DIN-rail mounted meter with segmented LCD and optional color TFT overlay for tariff visualization and grid event logging. IC Role / Device Role / Timing Role: Trusted execution environment for revenue-grade metrology calculations, secure key storage, and anti-tamper response logic. Use Value: Active tampers detect enclosure breach and erase sensitive keys; 512-byte OTP stores calibration constants with write-protection. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32U575ZIT6 | Same core and security, but 2 MB Flash, 1 MB SRAM, no MIPI DSI or Neo-Chrom GPU | Suitable for non-graphic secure endpoints (e.g., smart locks, gateways) where display acceleration is unnecessary | Select when display capability is not required and BOM cost reduction is prioritized over graphics throughput. |
| NXP i.MX RT685 | Arm Cortex-M33, 1 MB SRAM, no TrustZone-enforced flash protection, lacks LPBAM and sub-µA shutdown modes | Better suited for audio-centric edge AI (integrated audio DSP) but requires external PMIC for ultra-low-power operation | Prefer for voice-enabled devices needing integrated audio pre-processing; avoid when <500 nA standby or hardware-secured boot is mandatory. |
Compared with STM32U575ZIT6, the STM32U595ZIT6Q adds MIPI DSI, GPU2D, and 2× more SRAM for richer UIs; versus i.MX RT685, it delivers superior ultra-low-power autonomy and certified secure boot-critical for battery-operated certified medical or utility metering designs.
Availability
STM32U595ZIT6Q is available at Aetrix Electronics and suitable for industrial HMI, secure wireless sensor nodes, medical wearables, and smart energy metering requiring stable component supply across long-lifecycle deployments.
Supply support for STM32U595ZIT6Q includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and automotive semiconductors since 1987.
The STM32U5 series targets ultra-low-power secure edge computing, combining Arm TrustZone with ST's FlexPowerControl and LPBAM to enable decade-long battery life in certified IoT endpoints.
FAQ
What is the maximum operating temperature range for the STM32U595ZIT6Q?
The STM32U595ZIT6Q is rated for operation from –40 °C to +125 °C ambient temperature. This extended range is validated per ST's production data (DS13633 Rev 3), making it suitable for under-hood automotive modules, industrial drives, and outdoor metering enclosures without derating.
Does the STM32U595ZIT6Q support hardware-accelerated cryptography beyond HASH?
No - the STM32U595ZIT6Q integrates a dedicated HASH accelerator and NIST SP800-90B-compliant TRNG, but does not include AES, PKA, or ECC accelerators. Cryptographic operations beyond hashing require software implementation or external secure elements, as confirmed in Section 3.42–3.43 of DS13633 Rev 3.
Can the MIPI DSI interface drive a 1080p display?
No - the MIPI DSI host controller supports two lanes at up to 500 Mbit/s each (1 Gbit/s aggregate), sufficient for ≤800×480@60 Hz or ≤1280×800@30 Hz with compression. Driving native 1080p requires ≥2.1 Gbit/s bandwidth, exceeding this device's PHY capability, as specified in Section 3.40 and Table 135 of DS13633 Rev 3.
How many wake-up pins are available in Shutdown mode?
The STM32U595ZIT6Q provides 24 dedicated wake-up pins in Shutdown mode, all capable of generating interrupts from the 150 nA state. These include all GPIOs configured as EXTI inputs, as documented in Section 3.9.3 ("Low-power modes") and Table 102 of DS13633 Rev 3.
STM32U595ZIT6Q Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 144-LQFP
- Series:
- STM32U5
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 160MHz
- Connectivity:
- CANbus, I2C, IrDA, LINbus, MMC/SD/SDIO, SAI, SmartCard, SPDIF, SPI, UART/USART, USB, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, LCD, Motor Control PWM, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 2.5M x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 22x12/14b SAR; D/A 2x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32U595ZIT6Q FAQ
1.How can I place an order for STM32U595ZIT6Q through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32U595ZIT6Q on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32U595ZIT6Q reliable?
The price and inventory of STM32U595ZIT6Q are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32U595ZIT6Q is usually 5 days.
3.What payment methods are accepted for STM32U595ZIT6Q?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32U595ZIT6Q transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32U595ZIT6Q?
STM32U595ZIT6Q orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32U595ZIT6Q order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32U595ZIT6Q?
For technical support, including STM32U595ZIT6Q datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32U595ZIT6Q requirements.
6.How does Aetrix verify that STM32U595ZIT6Q is sourced from the original manufacturer or authorized distributors?
All STM32U595ZIT6Q products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32U595ZIT6Q meets industry standards.
7.What is the process for return or replacement of STM32U595ZIT6Q?
All STM32U595ZIT6Q units undergo pre-shipment inspection (PSI). If there is an issue with STM32U595ZIT6Q, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32U595ZIT6Q part is unused and in its original packaging.
Return procedure for STM32U595ZIT6Q:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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