STMicroelectronics STM32U595ZJT6

Overview

STM32U595ZJT6 from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit MCU with TrustZone® and FPU, delivering 240 DMIPS at up to 160 MHz. It integrates 4 MB Flash with ECC, 2.5 MB SRAM (with configurable ECC), MIPI® DSI host controller, LTDC, Neo-Chrom GPU, and operates from 1.71 V to 3.6 V across –40 °C to +125 °C. It targets secure, graphics-rich battery-powered edge devices such as smart medical wearables and industrial HMIs.

For engineers reviewing the STM32U595ZJT6 datasheet, STM32U595ZJT6 pinout, STM32U595ZJT6 application, or STM32U595ZJT6 equivalent, key selection criteria include TrustZone-enabled secure boot, LPBAM autonomous peripheral operation in Stop 2 mode, 18.5 µA/MHz Run-mode efficiency, and dual Octo-SPI interfaces for external memory expansion.

Technical Context

The device implements a dual-cache architecture with 32-Kbyte ICACHE and two 16-Kbyte DCACHEs-one for external memories and one dedicated to graphics acceleration-enabling zero-wait-state execution and efficient GPU2D/Chrom-ART operations. Its FlexPowerControl system supports dynamic voltage scaling between LDO and SMPS, with on-the-fly switching and five low-power modes down to 150 nA Shutdown.

TrustZone security is hardware-enforced across memory (Flash/SRAM), peripherals (GPIO, ADC, timers), and boot flow, backed by secure hide-protection area (HDP), root of trust, and TF-M–compatible secure firmware upgrade. The cryptographic suite includes HASH accelerator, NIST SP800-90B–compliant TRNG, and 96-bit unique ID.

Key Specifications

Pinout & Package

LQFP144 (20 × 20 mm, 0.5 mm pitch) package with 156 fast I/Os - 5V-tolerant on most pins, 14 I/Os support independent 1.08 V supply for ultra-low-voltage interface domains.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.

Compared with STM32U575ZIT6, the STM32U595ZJT6 adds MIPI DSI, GPU2D, and 2× more Flash/SRAM - essential for rich GUIs; versus i.MX RT685, it delivers 3.7× lower Stop 2 current and hardware-enforced TrustZone memory isolation - critical for certified secure deployments.

Availability

STM32U595ZJT6 is available at Aetrix Electronics and suitable for smart medical wearables, industrial HMI panels, USB-C powered edge gateways, and secure asset trackers requiring stable component supply across extended product lifecycles.

Supply support for STM32U595ZJT6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive semiconductors since 1987.

The STM32U5 series targets ultra-low-power, secure, and graphics-capable embedded applications - engineered for battery-operated edge devices demanding PSA Certified Level 3 security, ULPMark™-CP >360, and seamless human-machine interaction.

FAQ

What is the maximum operating temperature range for STM32U595ZJT6?

The STM32U595ZJT6 is qualified for operation from –40 °C to +125 °C ambient temperature, meeting industrial and extended-temperature requirements. This rating applies across all low-power modes and full peripheral functionality, including MIPI DSI and LTDC, as verified in DS13633 Rev 3 Section 5.3.1.

Does STM32U595ZJT6 support hardware-accelerated TLS 1.3?

Yes - the device achieves 120000 SecureMark™-TLS score via integrated HASH accelerator, TRNG, and optimized software stack on Cortex-M33. Hardware acceleration covers SHA-256, AES-128/256, and RSA/ECC crypto primitives required for TLS 1.3 handshake and record encryption, as documented in AN5507 and DS13633 Section 3.43.

How many wake-up pins are available in Shutdown mode?

The STM32U595ZJT6 provides 24 dedicated wake-up pins in Shutdown mode, all capable of generating interrupts from the 150 nA state. These include all GPIOs except those multiplexed exclusively for JTAG/SWD debug, and are configurable via the PWR_CR3 register per DS13633 Section 3.9.3.

Can the Neo-Chrom GPU2D render rotated bitmaps without CPU intervention?

Yes - Neo-Chrom GPU2D performs full-angle bitmap rotation, scaling, and perspective-correct texture mapping autonomously using its dedicated command FIFO and DMA engine. Rotation occurs in Stop 2 mode with no CPU involvement, as confirmed in RM0481 Section 3.19 and DS13633 Section 3.19, enabling always-on display updates at <1 mW.