STMicroelectronics STM32U599NIH6QTR

Overview

STM32U599NIH6QTR from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit MCU with TrustZone®, FPU, and FlexPowerControl - delivering 240 DMIPS at up to 160 MHz, 4 MB Flash with ECC, and 2.5 MB SRAM (ECC-configurable). It integrates LTDC, MIPI® DSI host controller (dual 500 Mbit/s lanes), Neo-Chrom GPU2D, and dual 14-bit ADCs (2.5 Msps), targeting secure, graphics-rich IoT edge nodes and battery-powered HMI devices.

For engineers reviewing the STM32U599NIH6QTR datasheet, STM32U599NIH6QTR pinout, STM32U599NIH6QTR application, or STM32U599NIH6QTR equivalent, key selection criteria include TrustZone-enabled secure boot, sub-µA Stop 2/3 modes (4.65 µA / 2 µA), 156 GPIOs (most 5V-tolerant), integrated SMPS + LDO, and hardware-accelerated crypto (HASH, RNG, CORDIC, FMAC).

Technical Context

The STM32U599NIH6QTR implements a dual-cache Arm Cortex-M33 core (32 KB ICACHE + 16 KB DCACHE1) enabling zero-wait-state execution from Flash at 160 MHz. Its TrustZone architecture enforces strict isolation between secure and non-secure firmware domains, with GTZC managing memory/peripheral access rights and RDP-based life-cycle control.

Power management combines embedded SMPS step-down converter (switch-on-the-fly), low-power background autonomous mode (LPBAM), and VBAT domain supporting RTC, 32×32-bit backup registers, and 2 KB backup SRAM. Graphics subsystem includes Chrom-ART DMA2D, Chrom-GRC (GFXMMU), and MIPI DSI host controller compliant with D-PHY v1.2.

Key Specifications

Pinout & Package

LQFP100 (14 × 14 mm, 0.5 mm pitch) package with 100 leads. Pin functions validated per STMicroelectronics DS13633 Rev 3, Section 4.2 (Pin description) and Table 17 (Pinout for LQFP100).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.

Compared with STM32U575ZIT6Q, the STM32U599NIH6QTR adds MIPI DSI, GPU2D, and double the Flash/SRAM - essential for graphics-rich secure edge devices. Versus i.MX RT600, it provides on-die SMPS, hardware TrustZone isolation, and lower static power - critical for battery longevity and certification readiness.

Availability

STM32U599NIH6QTR is available at Aetrix Electronics and suitable for secure IoT gateways, medical point-of-care monitors, and ultra-low-power environmental sensor nodes requiring stable component supply across multi-year production cycles.

Supply support for STM32U599NIH6QTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, MEMS, and automotive semiconductors.

The STM32U5 series is ST's flagship ultra-low-power secure MCU line, engineered for battery-operated edge AI, certified secure IoT endpoints, and graphics-capable human-machine interfaces demanding PSA Level 3 and IEC 62443 compliance.

FAQ

What is the maximum operating temperature range for STM32U599NIH6QTR?

The STM32U599NIH6QTR is rated for industrial operation from –40 °C to +85 °C, with extended qualification up to +125 °C for specific variants. This rating is confirmed in Section 5.3.1 of DS13633 Rev 3 and applies to the LQFP100 package under specified voltage and load conditions.

Does STM32U599NIH6QTR support hardware-accelerated TLS 1.3?

Yes - the device integrates HASH (SHA-256), TRNG (NIST SP800-90B compliant), and secure key storage (HDP, OTP) required for TLS 1.3 handshake acceleration. When paired with TF-M and secure bootloader, it achieves full TLS 1.3 stack offload in TrustZone-protected environment.

Can the MIPI DSI interface drive a 1080p display?

Yes - with two DSI lanes operating at 500 Mbit/s each (1 Gbit/s aggregate), the interface supports up to WUXGA (1920×1200) at 60 Hz using video mode. Pixel clock derivation and timing constraints are defined in Section 5.3.33 (MIPI D-PHY characteristics) of DS13633 Rev 3.

How does LPBAM reduce firmware development complexity?

LPBAM enables autonomous peripheral chaining (e.g., ADC → DMA → memory → timer) without CPU intervention, even in Stop 2 mode. Developers configure sequences via HAL drivers or STM32CubeMX; the hardware executes them independently - eliminating polling/interrupt overhead and simplifying low-power state machine design.