STMicroelectronics STM32U599NJH6Q

Overview

STM32U599NJH6Q from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit microcontroller with TrustZone® security, FPU, and integrated graphics acceleration (Neo-Chrom GPU + Chrom-ART), delivering 240 DMIPS at up to 160 MHz. It features 4 MB Flash with ECC, 2.5 MB SRAM (with configurable ECC), MIPI® DSI host controller (dual 500 Mbit/s lanes), LTDC, and operates from 1.71–3.6 V across –40 °C to +125 °C. It targets secure, high-resolution display-enabled IoT edge nodes requiring autonomous low-power operation.

For engineers reviewing the STM32U599NJH6Q datasheet, STM32U599NJH6Q pinout, STM32U599NJH6Q application, or STM32U599NJH6Q equivalent, key selection considerations include TrustZone-enforced memory partitioning, LPBAM peripheral autonomy in Stop 2 mode, dual DSI lane timing compliance, SRAM3 ECC configuration impact on usable RAM size, and UFBGA132 thermal/mechanical layout constraints.

Technical Context

The device implements a dual-bank Flash architecture enabling read-while-write with ECC, and supports voltage scaling via embedded SMPS/LDO for dynamic power optimization. Its TrustZone security model enforces strict isolation between secure/non-secure worlds at boot, runtime, and peripheral access levels - validated by hardware root of trust, HDP, and SFI support.

Graphics subsystem integration includes Neo-Chrom GPU (GPU2D) for rotation/scaling, Chrom-ART (DMA2D) for alpha-blending, and Chrom-GRC (GFXMMU) for resource-aware memory mapping - all operating under independent clock domains synchronized to the LTDC/DSI timing engine.

Key Specifications

Pinout & Package

STM32U599NJH6Q is housed in a 132-ball UFBGA package (7 × 7 mm, 0.5 mm pitch) with 156 fast I/Os - most 5V-tolerant, up to 14 supporting independent supply down to 1.08 V. Pin functions include dual DSI lanes (CLK/0–1), LTDC signals (HSYNC/VSYNC/DATA[23:0]), USB OTG HS (ULPI or PHY mode), and dedicated TrustZone-secured debug (SWDIO/SWCLK).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.

Compared with STM32U599NJH6Q, STM32U585AIK6Q sacrifices display subsystems and half the memory for lower cost and power, while i.MX RT600 trades integrated security and graphics for superior DSP performance and external memory flexibility - making STM32U599NJH6Q optimal for secure, battery-efficient, high-fidelity display applications.

Availability

STM32U599NJH6Q is available at Aetrix Electronics and suitable for smart utility meters, industrial HMIs, medical wearables, and connected building sensor hubs requiring stable component supply, long-term lifecycle assurance, and full production traceability.

Supply support for STM32U599NJH6Q includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive-grade components since 1987.

The STM32U5 series is engineered for ultra-low-power, secure, and graphics-rich IoT endpoints - combining Arm TrustZone, advanced power gating, and integrated display engines to eliminate external GPU and PMIC dependencies in battery-constrained designs.

FAQ

What is the maximum operating temperature rating for STM32U599NJH6Q?

The STM32U599NJH6Q is qualified for industrial operation from –40 °C to +125 °C ambient temperature. This extended range is validated per JEDEC JESD22-A104 and applies to all operating modes, including full-speed 160 MHz execution and DSI video streaming. Thermal derating begins above 105 °C in continuous Run mode.

Does STM32U599NJH6Q support hardware-based secure boot with public-key verification?

Yes. The device implements a hardware-rooted secure boot flow using immutable ROM code that verifies the signature of the first-stage bootloader (in System Memory or Flash) against ECDSA-P256 keys stored in the HDP (Hidden Protection Area). Public keys are provisioned during manufacturing and cannot be modified in the field.

Can the Neo-Chrom GPU operate independently of the CPU core during low-power modes?

No. The Neo-Chrom GPU requires the AHB bus matrix and associated clocks to be active, limiting its use to Run, Sleep, and Stop 1 modes. However, Chrom-ART (DMA2D) can execute blit operations autonomously in Stop 2 mode when triggered by LPDMA, enabling partial UI refresh without CPU wake-up.

How many wake-up pins are available in Shutdown mode, and what is their electrical behavior?

STM32U599NJH6Q provides 24 dedicated wake-up pins in Shutdown mode, each configurable as edge-sensitive (rising/falling/both) with internal pull-up/pull-down. These pins retain Schmitt-trigger input thresholds and operate at VDD voltage level - no external biasing required. Wake-up latency is guaranteed ≤5 µs from event detection to CPU reset release.