STMicroelectronics STM32U599NJH6QTR
- Part No.:
- STM32U599NJH6QTR
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 216-TFBGA
- Datasheet:
-
STM32U599NJH6QTR.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 216TFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
STM32U599NJH6QTR from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit MCU with TrustZone®, FPU, and integrated graphics acceleration (Neo-Chrom GPU, Chrom-ART), delivering 240 DMIPS at up to 160 MHz. It features 4 MB Flash with ECC, 2.5 MB SRAM (with configurable ECC), MIPI® DSI host controller (2 lanes @ 500 Mbit/s), LTDC, and operates from 1.71–3.6 V across –40 °C to +125 °C - designed for secure, battery-powered HMI applications in industrial gateways and portable medical displays.
For engineers reviewing the STM32U599NJH6QTR datasheet, STM32U599NJH6QTR pinout, STM32U599NJH6QTR application, or STM32U599NJH6QTR equivalent, key selection criteria include TrustZone-enabled secure boot, LPBAM autonomous peripheral operation in Stop 2 mode, dual 14-bit ADCs (2.5 Msps), 12-bit DAC with Stop 2 autonomy, and MIPI DSI + LTDC co-processing capability for high-fidelity embedded displays.
Technical Context
The device implements a dual-cache architecture with 32-Kbyte ICACHE and two independent 16-Kbyte DCACHEs (DCACHE1 for external memory, DCACHE2 for graphics), enabling zero-wait-state execution and efficient GPU/2D-accelerator data flow. Its FlexPowerControl system supports seven low-power modes - including 195 nA Standby and 480 nA Standby-with-RTC - managed via hardware-controlled voltage scaling between LDO and SMPS regulators.
Security is enforced through Arm TrustZone® partitioning of memory, peripherals, and I/Os, backed by a root-of-trust boot sequence, 512-byte OTP, 96-bit unique ID, and embedded HASH/RNG compliant with NIST SP800-90B. The GTZC (Global TrustZone Controller) enforces privilege-level access to all protected resources without software overhead.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone®, FPU, MPU, DSP extensions - enables secure real-time control with cryptographic isolation and deterministic floating-point math. |
| Max Clock / Performance | 160 MHz / 240 DMIPS - supports complex UI rendering and sensor fusion while maintaining sub-20 µA/MHz active efficiency. |
| Memory | 4 MB Flash (ECC, RWW), 2.5 MB SRAM (configurable ECC) - allows over-the-air firmware updates with fault-tolerant storage and large framebuffer allocation. |
| Graphics Interface | MIPI DSI host (2 lanes @ 500 Mbit/s) + LTDC + Neo-Chrom GPU2D - drives high-resolution RGB or DSI panels with hardware-accelerated rotation, scaling, and texture mapping. |
| Analog Peripherals | 2× 14-bit ADC (2.5 Msps), 1× 12-bit ADC (2.5 Msps, Stop 2 autonomous), 2× 12-bit DAC, 2× OPAMP, 2× COMP - supports simultaneous multi-sensor acquisition and analog actuation with ultra-low-power wake-up capability. |
| Low-Power Modes | 150 nA Shutdown, 480 nA Standby-with-RTC, 2 µA Stop 3 (40 KB SRAM retained) - extends battery life in always-on edge nodes with fast wake-up (<5 µs from Stop 2). |
| Security Features | TrustZone®, secure boot, HDP, SFI, TF-M support, HASH, TRNG (NIST SP800-90B) - meets PSA Certified Level 3 and SESIP requirements for IoT endpoint authentication and firmware integrity. |
Pinout & Package
This device is housed in a 208-pin WLCSP package (5.38 × 5.47 mm, 0.4 mm pitch), optimized for space-constrained portable HMI designs. Pin functions are validated per STMicroelectronics DS13633 Rev 3, Section 4.2 (Pin description) and Table 121 (Pin listing for WLCSP208).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDIO2 | Main and I/O supply rails | Dual 1.71–3.6 V supplies enable independent I/O voltage scaling down to 1.08 V for interfacing with legacy logic or low-voltage sensors. |
| VSS | Digital ground reference | Multiple dedicated VSS pins ensure low-impedance return paths for high-speed digital and analog domains, reducing noise coupling. |
| PA0–PA15, PB0–PB15, etc. | General-purpose I/Os | Up to 156 fast I/Os - 14 support independent 1.08–3.6 V supply; most are 5 V-tolerant, simplifying level-shifting in mixed-voltage systems. |
| DSI_D0P/N, DSI_D1P/N, DSI_CLKN/P | MIPI DSI differential lanes & clock | Hardware-terminated DSI PHY supports 500 Mbit/s per lane - eliminates external termination and reduces EMI in display interconnects. |
| LTDC_R0–R7, G0–G7, B0–B7, HSYNC/VSYNC/DE | RGB parallel interface outputs | Direct connection to TFT panels without external timing controller - enables low-latency, high-bandwidth display driving up to XGA resolution. |
| BOOT0 | Boot mode selection | Pulled low during reset to select main Flash boot; critical for field firmware recovery and secure boot enforcement. |
Key Features
| Feature | Design Value |
|---|---|
| LPBAM (Low-Power Background Autonomous Mode) | Enables DMA-driven peripheral chains (ADC→DMA→SRAM→DAC) fully autonomous in Stop 2 mode - eliminates CPU wake-ups for sensor logging or waveform generation. |
| Neo-Chrom GPU2D + Chrom-ART Accelerator | Hardware-accelerated 2D graphics pipeline supporting perspective-correct texture mapping and alpha-blending - reduces CPU load by >70 % in GUI rendering tasks. |
| Chrom-GRC (GFXMMU) | Graphics resource compression engine delivering up to 20 % bandwidth reduction on frame buffer transfers - extends effective SRAM capacity for high-color-depth displays. |
| Secure Firmware Installation (SFI) | Root-secured service enabling authenticated, encrypted firmware installation using embedded RSS - prevents unauthorized code injection during manufacturing or field update. |
| CORDIC + FMAC coprocessors | Hardware trigonometric (sin/cos/tan) and filter math acceleration - cuts FFT-based signal processing latency by 4× vs. software-only implementation. |
Applications
| Industrial HMI Panel | Portable Medical Monitor |
|---|---|
Use Scenario: Touch-enabled operator interface for PLC-controlled machinery with real-time alarm visualization and trend graphs. IC Role / Device Role / Timing Role: Primary application processor executing FreeRTOS-based GUI stack, managing MIPI DSI display, LTDC timing, and dual ADC sampling of temperature/pressure sensors. Use Value: LPBAM autonomously logs sensor data to SRAM during Stop 2, enabling <1 µA average current draw between HMI interactions while preserving full context for instant resume. | Use Scenario: Battery-powered patient monitor displaying ECG waveforms, SpO₂ trends, and vital signs on a 4.3″ WVGA LCD panel. IC Role / Device Role / Timing Role: System-on-chip handling analog front-end (dual 14-bit ADCs), display controller (LTDC + DSI), secure data logging, and Bluetooth LE connectivity. Use Value: 480 nA Standby-with-RTC ensures >5-year shelf life on coin cell; TrustZone isolates ECG algorithm code from BLE stack to meet IEC 62304 Class C safety requirements. |
| Smart Energy Gateway | Secure Access Terminal |
Use Scenario: DIN-rail mounted gateway aggregating smart meter data via RS-485, LoRaWAN, and Ethernet, with local web UI. IC Role / Device Role / Timing Role: Secure application host running Linux Lite or Zephyr, managing crypto operations (HASH/RNG), secure OTA updates, and dual SDMMC interfaces for local storage and removable media. Use Value: Dual Octo-SPI interfaces support simultaneous boot from one flash and firmware storage in another - enabling A/B update schemes with atomic rollback. | Use Scenario: Tamper-resistant physical access terminal using fingerprint + NFC authentication, with encrypted credential storage and audit logging. IC Role / Device Role / Timing Role: Root-of-trust controller enforcing secure boot, managing HDP-protected keys, and driving capacitive touch + OLED display via MIPI DSI. Use Value: Active tamper detection (voltage, frequency, temperature) triggers immediate SRAM wipe and secure state lockdown - meeting Common Criteria EAL5+ physical attack resistance requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32U585AIK6QTR | Same U5 series, but 2 MB Flash, 1 MB SRAM, no MIPI DSI, no Neo-Chrom GPU - lacks display acceleration and high-res graphics support. | Suitable for secure sensor hubs or crypto gateways without display output - not viable for HMI or medical display use cases. | Select when display subsystem is unnecessary and cost/size optimization is prioritized over graphical capability. |
| NXP i.MX RT600 | Arm Cortex-M33 + DSP core, 1 MB SRAM, no TrustZone-enforced peripheral security, no LPBAM, no integrated DSI/LTDC - relies on external display controllers. | Targeted at audio DSP + lightweight GUI (e.g., voice assistant endpoints), not safety-critical or battery-optimized display systems. | Prefer only if existing NXP toolchain investment outweighs need for ST's ultra-low-power graphics stack and certified security architecture. |
Compared with STM32U585AIK6QTR and i.MX RT600, the STM32U599NJH6QTR uniquely integrates MIPI DSI + LTDC + GPU2D with sub-500 nA standby and TrustZone-managed peripheral isolation - making it the only option among the three qualified for battery-powered, safety-certifiable, high-fidelity embedded displays.
Availability
STM32U599NJH6QTR is available at Aetrix Electronics and suitable for industrial HMI panels, portable medical monitors, smart energy gateways, and secure access terminals requiring stable component supply across extended product lifecycles.
Supply support for STM32U599NJH6QTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in microcontrollers, power management, sensors, and automotive ICs - with over 40 years of embedded systems innovation.
The STM32U5 series targets ultra-low-power, secure, and graphics-capable edge devices - designed specifically for battery-operated industrial, medical, and consumer applications demanding PSA Level 3 certification and long-term supply stability.
FAQ
What is the maximum operating temperature range for STM32U599NJH6QTR?
The device is rated for –40 °C to +125 °C ambient operation, validated per DS13633 Rev 3 Section 5.3.1. This extended grade supports deployment in harsh industrial enclosures and automotive under-hood auxiliary modules where thermal management is constrained.
Does STM32U599NJH6QTR support hardware-accelerated cryptography?
It includes a dedicated HASH hardware accelerator supporting SHA-1, SHA-224, and SHA-256 algorithms, plus a NIST SP800-90B-compliant true random number generator (TRNG). No AES engine is integrated - AES operations rely on software libraries or external secure elements.
Can the MIPI DSI interface drive a 1080p display?
No - the dual-lane DSI host supports up to 500 Mbit/s per lane (1 Gbit/s total), sufficient for WVGA (800×480) or HD (1280×720) at 60 Hz with 24-bit color. Driving native 1080p requires ≥2.1 Gbit/s bandwidth, exceeding this device's PHY capability.
Is the WLCSP208 package compatible with standard reflow profiles?
Yes - the WLCSP208 package (5.38 × 5.47 mm, 0.4 mm pitch) is qualified for IPC/JEDEC J-STD-020D reflow, with peak temperature tolerance up to 260 °C. ST recommends using solder paste with Type 4 or finer particles and controlled ramp rates to prevent die cracking.
STM32U599NJH6QTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 216-TFBGA
- Series:
- STM32U5
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 160MHz
- Connectivity:
- CANbus, I2C, IrDA, LINbus, MMC/SD/SDIO, SAI, SmartCard, SPDIF, SPI, UART/USART, USB, USB OTG
- Peripherals:
- Brown-out Detect/Reset, DMA, LCD, Motor Control PWM, POR, PWM, WDT
- Number of I/O:
- 156
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 2.5M x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 24x12/14b SAR; D/A 2x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32U599NJH6QTR FAQ
1.How can I place an order for STM32U599NJH6QTR through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32U599NJH6QTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32U599NJH6QTR reliable?
The price and inventory of STM32U599NJH6QTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32U599NJH6QTR is usually 5 days.
3.What payment methods are accepted for STM32U599NJH6QTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32U599NJH6QTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32U599NJH6QTR?
STM32U599NJH6QTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32U599NJH6QTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32U599NJH6QTR?
For technical support, including STM32U599NJH6QTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32U599NJH6QTR requirements.
6.How does Aetrix verify that STM32U599NJH6QTR is sourced from the original manufacturer or authorized distributors?
All STM32U599NJH6QTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32U599NJH6QTR meets industry standards.
7.What is the process for return or replacement of STM32U599NJH6QTR?
All STM32U599NJH6QTR units undergo pre-shipment inspection (PSI). If there is an issue with STM32U599NJH6QTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32U599NJH6QTR part is unused and in its original packaging.
Return procedure for STM32U599NJH6QTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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