Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Embedded > Microcontrollers

STMicroelectronics STM32U5A5AJH3

Name: STM32U5A5AJH3
Brand: STMicroelectronics
SKU: STM32U5A5AJH3
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: STM32U5A5AJH3

Manufacturer:: STMicroelectronics

Category:: Microcontrollers

Package:: 169-TFBGA

Datasheet:: STM32U5A5AJH3.pdf

Description:: IC MCU 32BIT 4MB FLASH 169TFBGA

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,753

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

STM32U5A5AJH3 from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit microcontroller with TrustZone® security, 4 MB Flash, 2.5 MB SRAM, MIPI® DSI host controller, LTDC, and hardware crypto accelerators. It operates from 1.71 V to 3.6 V across –40 °C to +125 °C and delivers 240 DMIPS at up to 160 MHz-targeted for secure, graphics-rich battery-powered industrial HMI and smart sensor edge nodes.

For engineers reviewing the STM32U5A5AJH3 datasheet, STM32U5A5AJH3 pinout, STM32U5A5AJH3 application, or STM32U5A5AJH3 equivalent, key selection criteria include TrustZone-enabled secure boot, LPBAM autonomous peripheral operation in Stop 2 mode, 18.5 µA/MHz Run-mode efficiency, and dual Octo-SPI interfaces for encrypted external memory expansion.

Technical Context

The device integrates a dual-cache Arm Cortex-M33 core (32 KB I-Cache, 16 KB D-Cache1) with TrustZone isolation, enabling secure firmware partitioning and hardware-enforced privilege separation between secure/non-secure worlds. Its FlexPowerControl architecture supports five low-power modes-including 480 nA Standby with RTC and 2 µA Stop 3 with 40 KB SRAM-managed via embedded SMPS and LDO regulators with on-the-fly voltage scaling.

Graphics acceleration is implemented through Neo-Chrom GPU2D (rotation/scaling), Chrom-ART DMA2D (transparency/motion), and Chrom-GRC GFXMMU (20% resource optimization). Security includes SESIP3/PSA Level 3 certification, two AES coprocessors (one DPA-resistant), PKA, HASH, OTFDEC, and NIST SP800-90B-compliant TRNG.

Key Specifications

Parameter	Value and Actual Design Meaning
CPU Core	Arm Cortex-M33 with TrustZone, FPU, MPU, DSP extensions - enables secure real-time control with deterministic floating-point math.
Max Clock / Performance	160 MHz / 240 DMIPS - achieves zero-wait-state execution from flash via ART Accelerator.
Memory	4 MB Flash (ECC, read-while-write), 2.5 MB SRAM (ECC configurable) - supports robust firmware storage and large buffer handling for graphics/audio.
Low-Power Modes	150 nA Shutdown, 480 nA Standby w/RTC, 2 µA Stop 3 w/40 KB SRAM - extends battery life in always-on sensing and display applications.
Security	SESIP3 & PSA Level 3 certified; TrustZone, HUK, SFI, TF-M support - meets requirements for secure OTA updates and root-of-trust boot.
Graphics Interfaces	MIPI DSI (2 lanes @ 500 Mbit/s), LTDC, Neo-Chrom GPU2D, DMA2D, GFXMMU - enables high-fidelity, low-CPU-load TFT displays up to WXGA resolution.
Analog Peripherals	Two 14-bit ADCs (2.5 Msps), one 12-bit ADC (autonomous in Stop 2), dual 12-bit DACs, 2 op-amps, 2 comparators - supports precision sensor acquisition with minimal active power.
Communication	1x CAN FD, 7x USART, 6x I²C, 3x SPI, 2x SDMMC, USB OTG HS, UCPD, 2x SAI - provides flexible connectivity for industrial gateways and multi-protocol edge devices.

Pinout & Package

LQFP100 (14 × 14 mm, 0.5 mm pitch) package with 100 pins. Pin functions include VDD/VSS power rails, 82 general-purpose I/Os (most 5 V-tolerant), 14 low-voltage I/Os (1.08–3.6 V), dedicated MIPI DSI/DSI clock, LTDC data/control, Octo-SPI/HSPI buses, USB OTG HS PHY, UCPD, and TrustZone-secured debug (SWD).

Pin/Terminal	Circuit Role	Design Meaning
VDD, VSS	Core & I/O power supply	Dual-domain supply enables independent I/O voltage scaling down to 1.08 V for interfacing with low-voltage peripherals.
PA0–PA15, PB0–PB15, etc.	General-purpose I/O	Up to 156 fast GPIOs with interrupt capability; most tolerate 5 V, supporting legacy interface compatibility.
PD0–PD15	LTDC data/control outputs	Direct parallel RGB interface for TFT-LCD panels up to 1024×768, synchronized with DMA2D for overlay composition.
PE2–PE11	MIPI DSI host lanes	Two high-speed DSI lanes (up to 500 Mbit/s each) with embedded clock for driving DSI-based displays without external timing ICs.
PF0–PF13	Octo-SPI/HSPI memory interface	Supports encrypted external NOR/PSRAM/NAND via OTFDEC; HSPI runs up to 160 MHz for high-bandwidth streaming.
PA11/PA12	USB OTG HS PHY	Integrated high-speed transceiver eliminates need for external PHY; supports full-speed and high-speed device/host operation.
PC13–PC15	RTC/LSE oscillator	32 kHz crystal input for calendar RTC with tamper detection and backup register retention in VBAT mode.
NRST	Active-low reset input	Asynchronous reset pin with internal pull-up; compatible with standard reset supervisor circuits and manual push-button reset.

Key Features

Feature	Design Value
LPBAM (Low-Power Background Autonomous Mode)	Enables DMA-driven peripheral chains (ADC→DMA→Crypto→SRAM) without CPU wake-up - reduces active time by >90% in sensor logging.
Neo-Chrom GPU2D + Chrom-ART DMA2D	Hardware-accelerated 2D graphics rendering offloads CPU for smooth UI transitions, alpha blending, and rotation - cuts frame-buffer CPU load by ~70%.
TrustZone + Secure Boot + HUK	Immutable root of trust with unique hardware key and secure hide-protection area - prevents firmware cloning and ensures cryptographic key confidentiality.
On-the-Fly Decryption (OTFDEC)	Decrypts Octo-SPI external memory contents in real time using AES-128/256 - enables secure code/data execution from external flash without RAM exposure.
CORDIC + FMAC Coprocessors	Accelerates trigonometric (sin/cos/tan) and digital filter (IIR/FIR) computations - improves motor control loop speed and audio preprocessing latency.

Applications

Industrial HMI Display

Secure Smart Sensor Node

Use Scenario: Battery-powered panel meter with color TFT display, touch interface, and local data logging.

IC Role / Device Role / Timing Role: Main application processor managing LTDC/DSI display, touch controller via TSC, and secure sensor fusion via LPBAM-enabled ADC/DAC chains.

Use Value: 18.5 µA/MHz Run mode and Stop 3 with 40 KB SRAM enable multi-week operation on coin-cell; GPU2D renders UI at 60 fps with <5% CPU load.

Use Scenario: Wireless predictive maintenance node monitoring vibration, temperature, and current in factory equipment.

IC Role / Device Role / Timing Role: Secure edge AI inference accelerator running TinyML models on sensor data, with encrypted OTA updates via TF-M and UCPD Type-C power delivery.

Use Value: TrustZone isolates ML model weights in secure SRAM; OTFDEC executes inference code directly from encrypted external PSRAM; 150 nA Shutdown extends field life beyond 10 years.

Medical Wearable Monitor

Automotive Cabin Controller

Use Scenario: CE-certified wearable ECG/SpO₂ monitor with OLED display and Bluetooth LE connectivity.

IC Role / Device Role / Timing Role: Real-time biosignal acquisition (14-bit ADC @ 2.5 Msps), analog front-end (op-amps + comparators), and secure BLE stack execution in non-secure world.

Use Value: Autonomous Stop 2 mode with 12-bit ADC allows continuous sampling at 1 kSPS while consuming only 4.65 µA - meets ISO 13485 low-power compliance.

Use Scenario: In-cabin infotainment sub-module controlling ambient lighting, HVAC feedback, and capacitive touch controls.

IC Role / Device Role / Timing Role: Graphics co-processor rendering dynamic lighting effects via LTDC + DMA2D, while CAN FD communicates with main head unit and UCPD manages USB-C accessory power negotiation.

Use Value: Dual Octo-SPI interfaces store lighting animation assets and firmware images separately; PSA Level 3 cert satisfies automotive cybersecurity audit requirements (UNECE R155).

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
STM32U575ZIT6	Same U5A series core, but 2 MB Flash, 1 MB SRAM, no MIPI DSI, no Neo-Chrom GPU - lacks display acceleration and external memory bandwidth.	Suitable for secure sensor hubs without graphics; not viable for DSI/LTDC-based HMIs.	Select when display capability is unnecessary and BOM cost reduction is prioritized over graphics throughput.
NXP i.MX RT600	Arm Cortex-M33 + DSP, 1 MB SRAM, no TrustZone-certified crypto accelerators, no LPBAM, higher active current (25 µA/MHz).	Targeted at audio DSP workloads; lacks certified secure boot and ultra-low-power autonomous modes.	Choose only if existing NXP SDK ecosystem and audio-focused peripherals (e.g., PDM mic interfaces) outweigh security and power advantages.

Compared with STM32U5A5AJH3, STM32U575ZIT6 sacrifices display capability and memory capacity for lower cost, while i.MX RT600 trades certified security and sub-µA low-power states for higher DSP compute density - making STM32U5A5AJH3 uniquely balanced for secure, graphics-enabled edge endpoints.

Availability

STM32U5A5AJH3 is available at Aetrix Electronics and suitable for industrial HMI, medical wearables, automotive cabin controllers, and secure smart sensor nodes requiring stable component supply across extended product lifecycles.

Supply support for STM32U5A5AJH3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog components for industrial, automotive, and consumer markets.

The STM32U5 series targets next-generation ultra-low-power, secure, and graphics-capable edge devices - combining Arm TrustZone, advanced power gating, and hardware-accelerated 2D graphics to replace discrete display controllers and reduce system-level BOM cost.

FAQ

What is the maximum operating temperature rating for STM32U5A5AJH3?

The STM32U5A5AJH3 is rated for operation from –40 °C to +125 °C, qualified per AEC-Q100 Grade 1 for automotive under-hood and industrial environments. This extended range is enabled by ST's proprietary process technology and thermal-aware power management, including adaptive voltage scaling and SMPS regulation.

Does STM32U5A5AJH3 support external memory encryption at runtime?

Yes - the on-the-fly decryption engine (OTFDEC) supports AES-128/256 decryption of Octo-SPI external memories in real time, with keys stored in secure SRAM or derived from the hardware unique key (HUK). Decrypted code executes directly from external memory without exposing plaintext in internal RAM.

Can the MIPI DSI interface drive a 1080p display?

No - the MIPI DSI host controller supports up to two lanes at 500 Mbit/s each (1 Gbit/s total), sufficient for WVGA (800×480) or WXGA (1280×800) panels at 60 Hz. Driving native 1080p requires ≥2.1 Gbit/s bandwidth; this device targets mid-resolution industrial and medical displays, not full HD video.

Is TrustZone configuration handled solely in firmware, or does it require hardware provisioning?

TrustZone security is enforced by hardware (GTZC controller) but configured at boot via immutable secure ROM code and user-defined settings in the secure option bytes. Initial provisioning requires programming RDP level and secure boot keys via SWD; once locked, configuration is immutable without mass erase - ensuring tamper-resistant isolation between secure and non-secure worlds.

STM32U5A5AJH3 Specifications

Product attributes: Attribute value

Manufacturer:: STMicroelectronics

Package/Case:: 169-TFBGA

Series:: STM32U5

Packaging:: Tray

Product Status:: Active

Programmable:: -

Core Processor:: ARM® Cortex®-M33

Core Size:: 32-Bit

Speed:: 160MHz

Connectivity:: CANbus, EBI/EMI, FIFO, I2C, IrDA, LINbus, MMC/SD, SPI, UART/USART/USB

Peripherals:: Brown-out Detect/Reset, Crypto - AES, DMA, PWM, SHA, Temp Sensor, TRNG, WDT

Number of I/O:: 136

Program Memory Size:: 4MB (4M x 8)

Program Memory Type:: FLASH

EEPROM Size:: -

RAM Size:: 2.5M x 8

Voltage - Supply (Vcc/Vdd):: 1.71V ~ 3.6V

Data Converters:: A/D 24x12/14b SAR; D/A 2x12b

Oscillator Type:: External, Internal

Operating Temperature:: -40°C ~ 125°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:

STM32U5A5AJH3 FAQ

1.How can I place an order for STM32U5A5AJH3 through Aetrix?

Please submit a Request for Quotation (RFQ) for STM32U5A5AJH3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for STM32U5A5AJH3 reliable?

The price and inventory of STM32U5A5AJH3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32U5A5AJH3 is usually 5 days.

3.What payment methods are accepted for STM32U5A5AJH3?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32U5A5AJH3 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for STM32U5A5AJH3?

STM32U5A5AJH3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your STM32U5A5AJH3 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for STM32U5A5AJH3?

For technical support, including STM32U5A5AJH3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32U5A5AJH3 requirements.

6.How does Aetrix verify that STM32U5A5AJH3 is sourced from the original manufacturer or authorized distributors?

All STM32U5A5AJH3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32U5A5AJH3 meets industry standards.

7.What is the process for return or replacement of STM32U5A5AJH3?

All STM32U5A5AJH3 units undergo pre-shipment inspection (PSI). If there is an issue with STM32U5A5AJH3, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The STM32U5A5AJH3 part is unused and in its original packaging.

Return procedure for STM32U5A5AJH3:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…