STMicroelectronics STM32U5A5QJI6
- Part No.:
- STM32U5A5QJI6
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 132-UFBGA
- Datasheet:
-
STM32U5A5QJI6.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 132UFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:2,902
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32U5A5QJI6 from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit MCU with TrustZone® and FPU, delivering 240 DMIPS at up to 160 MHz. It integrates 4 MB Flash with ECC, 2.5 MB SRAM (with configurable ECC), LTDC, MIPI® DSI host controller, Neo-Chrom GPU, and hardware crypto accelerators including AES, PKA, and HASH. It targets secure, graphics-rich IoT edge nodes requiring long battery life and real-time responsiveness.
For engineers reviewing the STM32U5A5QJI6 datasheet, STM32U5A5QJI6 pinout, STM32U5A5QJI6 application, or STM32U5A5QJI6 equivalent, key selection considerations include its dual-bank Flash with read-while-write capability, Stop 2 mode current of 4.65 µA (40 KB SRAM) or 17.5 µA (2.5 MB SRAM), TrustZone-secured peripheral isolation, and MIPI DSI support for high-resolution displays in constrained power envelopes.
Technical Context
The STM32U5A5QJI6 implements a dual-core security architecture via Arm TrustZone®, enabling strict separation of secure and non-secure firmware execution, memory regions, and peripheral access. Its FlexPowerControl system supports seven low-power modes-including Shutdown (150 nA), Standby (195 nA), and Stop 2 (4.65 µA)-with autonomous peripherals like LPDMA and LPTIM active down to Stop 2.
Graphics acceleration is handled by three dedicated blocks: Neo-Chrom GPU (GPU2D) for rotation/scaling, Chrom-ART Accelerator (DMA2D) for transparency and blending, and Chrom-GRC (GFXMMU) for resource optimization. The MIPI DSI host controller operates two lanes at up to 500 Mbit/s each, directly driving display panels without external bridge ICs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone, FPU, MPU, and DSP extensions - enables secure real-time control with floating-point math and memory protection. |
| Max Clock / Performance | 160 MHz / 240 DMIPS - supports demanding signal processing and UI rendering while maintaining sub-20 µA/MHz efficiency in Run mode. |
| Memory | 4 MB Flash (ECC, read-while-write), 2.5 MB SRAM (configurable ECC) - allows over-the-air firmware updates and large buffer storage for graphics/audio pipelines. |
| Low-Power Modes | Stop 2: 4.65 µA (40 KB SRAM) or 17.5 µA (2.5 MB SRAM); Shutdown: 150 nA - enables multi-year battery operation in sensor hubs and portable HMI devices. |
| Graphics Interface | MIPI DSI host (2 lanes @ 500 Mbit/s each) + LTDC + Neo-Chrom GPU - drives QHD+ displays directly with hardware-accelerated UI composition. |
| Crypto Acceleration | Dual AES coprocessors (one DPA-resistant), PKA, HASH, RNG (NIST SP800-90B), OTFDEC - enables TLS 1.3 handshake in <100 ms and secure boot with root-of-trust. |
| Analog Peripherals | Two 14-bit ADCs (2.5 Msps, hardware oversampling), 12-bit DAC (2 ch), 2 op-amps with PGA, 2 ultra-low-power comparators - supports precision sensor fusion and analog actuation in mixed-signal edge nodes. |
Pinout & Package
The STM32U5A5QJI6 is housed in a WLCSP208 package (5.38 × 5.47 mm), optimized for space-constrained portable and wearable applications. This ball-grid array variant supports fine-pitch routing and thermal performance suitable for high-density PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD | Main power supply (1.71–3.6 V) | Supplies core, I/O, and most peripherals; supports dynamic voltage scaling with SMPS/LDO coexistence. |
| VDDA | Analog domain supply | Independent 1.62–3.6 V rail for ADC/DAC/OPAMP - ensures noise isolation and stable reference accuracy. |
| VBAT | Backup power supply | Feeds RTC, 32 × 32-bit backup registers, and 2 KB backup SRAM during main power loss. |
| NRST | Active-low reset input | Asynchronous reset with internal pull-up; compatible with external reset supervisors and push-button recovery. |
| PA0–PA15, PB0–PB15, etc. | General-purpose I/Os | Up to 156 fast I/Os; most 5V-tolerant, 14 with independent supply down to 1.08 V - enables flexible interfacing with legacy and low-voltage peripherals. |
| DSI_D0P/N, DSI_D1P/N | MIPI DSI differential data lanes | High-speed differential pairs supporting up to 500 Mbit/s per lane - directly connect to DSI display modules without level-shifting. |
| LTDC_R0–R7, G0–G7, B0–B7, etc. | RGB parallel interface signals | Supports 24-bit RGB output for TFT-LCD panels; configurable for 8-/16-/24-bit formats and sync polarity. |
Key Features
| Feature | Design Value |
|---|---|
| TrustZone-enabled secure boot | Root-of-trust established via unique boot entry and secure hide-protection area (HDP), enabling certified PSA Level 3 and SESIP3 compliance. |
| LPBAM autonomous operation | Peripherals (ADC, timers, DMA) operate without CPU intervention in Stop 2 mode - reduces active time and extends battery life in sensor polling cycles. |
| On-the-fly Octo-SPI decryption | OTFDEC engine decrypts external flash contents in real time using AES-128/256 - eliminates need for RAM-based decryption buffers and protects firmware IP. |
| Neo-Chrom GPU + Chrom-ART | GPU2D handles affine transforms and texture mapping; DMA2D performs alpha blending and color conversion - offloads 80%+ of UI rendering from CPU. |
| Multi-rail I/O flexibility | 14 I/Os support independent VDDIO2 down to 1.08 V - simplifies interfacing with ultra-low-voltage sensors and logic without level shifters. |
Applications
| Smart Wearable Display | Secure Industrial Sensor Hub |
|---|---|
Use Scenario: A wrist-worn health monitor with always-on QHD OLED display and continuous ECG/PPG sensing. IC Role / Device Role / Timing Role: Main application processor managing display refresh (via MIPI DSI), sensor data acquisition (dual 14-bit ADCs), and cryptographic signing of biometric logs. Use Value: Stop 2 mode (4.65 µA w/ 40 KB SRAM) maintains RTC and sensor triggers while preserving display state; Neo-Chrom GPU renders smooth animations at <1 mW. | Use Scenario: Battery-powered predictive maintenance node monitoring vibration, temperature, and acoustic emissions in factory machinery. IC Role / Device Role / Timing Role: Edge AI inference accelerator using FMAC/CORDIC, secure OTA update handler (TF-M), and tamper-detecting RTC with backup SRAM. Use Value: Dual AES engines enable concurrent TLS 1.3 session + local firmware encryption; 17.5 µA Stop 2 mode sustains 2.5 MB sensor history buffer for offline analysis. |
| Medical Handheld Diagnostic Tool | Ultra-Low-Power Smart Home Gateway |
Use Scenario: Portable ultrasound assistant with touch-sensitive GUI, analog front-end, and Bluetooth LE connectivity. IC Role / Device Role / Timing Role: Real-time signal processor (CORDIC/FMAC), graphics compositor (LTDC + DMA2D), and secure BLE controller (via USB OTG HS + SAI). Use Value: 12-bit DAC and OPAMPs drive analog beamforming circuits; TrustZone isolates diagnostic algorithms from BLE stack to meet IEC 62304 Class C requirements. | Use Scenario: Wall-mounted Zigbee/Matter gateway with capacitive touch panel, ambient light sensing, and local voice preprocessing. IC Role / Device Role / Timing Role: Multi-protocol concentrator (FDCAN, 7x USART, 6x I²C), low-power audio frontend (SAI + ADF), and secure key store (HUK + OTP). Use Value: 195 nA Standby mode enables >5-year battery life; 512-byte OTP stores device-specific credentials; TSC supports 16-channel capacitive touch with <5 µA active current. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32U575ZIT6 | Same U5A series core, but 2 MB Flash, 1 MB SRAM, no MIPI DSI, no Neo-Chrom GPU - lacks display acceleration and external memory bandwidth. | Targeted at secure sensor nodes without graphics; lower BOM cost where display interface is unnecessary. | Select when display output is absent and crypto/security features suffice without GPU or DSI. |
| RA8T1A020FNE1 | Arm Cortex-M85 core, 2 MB Flash, 1.5 MB SRAM, no TrustZone, no MIPI DSI, no GPU - higher peak performance but no certified PSA Level 3 or hardware-accelerated graphics. | Optimized for motor control and real-time deterministic workloads; lacks display subsystem and ULPMark-PP benchmark parity. | Choose for high-CPU-throughput industrial control where display and ultra-low-power standby are secondary. |
Compared with STM32U575ZIT6 and RA8T1A020FNE1, the STM32U5A5QJI6 uniquely combines PSA Level 3 certification, MIPI DSI + LTDC + GPU2D graphics pipeline, and sub-20 µA Stop 2 operation - making it the only option for battery-powered, secure, high-resolution embedded displays requiring <10-year field deployment.
Availability
STM32U5A5QJI6 is available at Aetrix Electronics and suitable for smart wearables, medical handheld diagnostics, secure industrial gateways, and battery-powered HMI systems requiring stable component supply across multi-year production cycles.
Supply support for STM32U5A5QJI6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, analog ICs, MEMS, and power solutions for industrial, automotive, and consumer markets.
The STM32U5 series is ST's flagship ultra-low-power MCU line targeting secure, graphics-capable edge devices - engineered to deliver best-in-class ULPMark™ scores while integrating TrustZone, crypto accelerators, and display interfaces in a single die.
FAQ
What is the maximum operating temperature range for the STM32U5A5QJI6?
The STM32U5A5QJI6 is rated for operation from –40 °C to +125 °C, validated across full voltage (1.71–3.6 V) and performance ranges. This extended industrial temperature grade supports deployment in automotive cabin modules, industrial motor drives, and outdoor IoT infrastructure without derating.
Does the STM32U5A5QJI6 support external memory interfaces beyond Octo-SPI?
Yes - it integrates a Flexible Static Memory Controller (FSMC) supporting SRAM, PSRAM, NOR, NAND, and FRAM, plus two Octo-SPI interfaces and one 16-bit HSPI interface running up to 160 MHz. This enables direct attachment of high-bandwidth external memories for graphics frame buffers or firmware storage without external bus expanders.
How does the TrustZone implementation differ between STM32U5A5QJI6 and earlier STM32L5 devices?
The STM32U5A5QJI6 enhances TrustZone with Global TrustZone Controller (GTZC) v2, adding securable I/Os, enhanced peripheral classification, and tighter integration with PWR/RTC domains. Unlike STM32L5, it supports secure debug lockdown via RDP and password-protected access to HDP - meeting PSA Certified Level 3 and SESIP3 assurance requirements.
Can the Neo-Chrom GPU operate independently of the CPU during low-power modes?
No - the Neo-Chrom GPU requires CPU initialization and command list submission via AXI bus, and is clock-gated in Stop 2 and deeper modes. However, the Chrom-ART Accelerator (DMA2D) can execute preloaded 2D operations autonomously in Stop 2 mode when triggered by LPDMA, enabling partial UI updates without CPU wake-up.
STM32U5A5QJI6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 132-UFBGA
- Series:
- STM32U5
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 160MHz
- Connectivity:
- CANbus, EBI/EMI, FIFO, I2C, IrDA, LINbus, MMC/SD, SPI, UART/USART/USB
- Peripherals:
- Brown-out Detect/Reset, Crypto - AES, DMA, PWM, SHA, Temp Sensor, TRNG, WDT
- Number of I/O:
- 106
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 2.5M x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 18x12/14b SAR; D/A 2x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32U5A5QJI6 FAQ
1.How can I place an order for STM32U5A5QJI6 through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32U5A5QJI6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32U5A5QJI6 reliable?
The price and inventory of STM32U5A5QJI6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32U5A5QJI6 is usually 5 days.
3.What payment methods are accepted for STM32U5A5QJI6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32U5A5QJI6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32U5A5QJI6?
STM32U5A5QJI6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32U5A5QJI6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32U5A5QJI6?
For technical support, including STM32U5A5QJI6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32U5A5QJI6 requirements.
6.How does Aetrix verify that STM32U5A5QJI6 is sourced from the original manufacturer or authorized distributors?
All STM32U5A5QJI6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32U5A5QJI6 meets industry standards.
7.What is the process for return or replacement of STM32U5A5QJI6?
All STM32U5A5QJI6 units undergo pre-shipment inspection (PSI). If there is an issue with STM32U5A5QJI6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32U5A5QJI6 part is unused and in its original packaging.
Return procedure for STM32U5A5QJI6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32U5A5QJI6 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

