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STMicroelectronics STM32U5A5RJT6Q
- Part No.:
- STM32U5A5RJT6Q
- Manufacturer:
- STMicroelectronics
- Category:
- Microcontrollers
- Package:
- 64-LQFP
- Datasheet:
-
STM32U5A5RJT6Q.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 64LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:4,508
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Product details
Overview
STM32U5A5RJT6Q from STMicroelectronics is an ultra-low-power Arm® Cortex®-M33 32-bit microcontroller with TrustZone® and FPU, delivering 240 DMIPS at up to 160 MHz. It integrates 4 MB Flash with ECC, 2.5 MB SRAM (with configurable ECC), MIPI® DSI host controller, LTDC, Neo-Chrom GPU, and hardware crypto accelerators (AES, PKA, HASH, RNG). It targets secure, graphics-rich, battery-operated edge devices such as smart wearables and industrial HMIs.
For engineers reviewing the STM32U5A5RJT6Q datasheet, STM32U5A5RJT6Q pinout, STM32U5A5RJT6Q application, or STM32U5A5RJT6Q equivalent, key selection criteria include its 150 nA Shutdown mode, dual 14-bit ADCs (2.5 Msps), LPBAM autonomous peripheral operation in Stop 2, TrustZone-secured boot and memory partitioning, and MIPI DSI + LTDC support for embedded display subsystems.
Technical Context
The device implements a dual-bank Flash architecture enabling read-while-write operations and supports on-the-fly voltage scaling between 1.1 V and 1.26 V via integrated SMPS and LDO regulators. Its low-power design centers on FlexPowerControl, with LPBAM enabling DMA-driven peripheral chains (e.g., ADC→DMA→Crypto) without CPU intervention down to Stop 2 mode.
TrustZone enforces hardware-isolated secure/non-secure worlds: secure boot starts from immutable ROM, HDP protects secure firmware, and GTZC gates access to memories/peripherals. The Neo-Chrom GPU and Chrom-ART Accelerator (DMA2D) offload 2D graphics rendering, while MIPI DSI (dual 500 Mbit/s lanes) and LTDC drive high-resolution TFT displays with hardware alpha blending and rotation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 with TrustZone, FPU, MPU, and DSP extensions - enables secure real-time control with floating-point math and memory isolation. |
| Max Clock / Performance | 160 MHz / 240 DMIPS - achieves zero-wait-state execution from Flash via 32-KB ICACHE and delivers 4.09 CoreMark®/MHz. |
| Memory | 4-MB Flash (ECC, 2-bank RWW), 2.5-MB SRAM (configurable ECC) - supports secure firmware updates and large buffer storage for graphics/audio processing. |
| Low-Power Modes | 150 nA Shutdown, 480 nA Standby w/RTC, 2 µA Stop 3 w/40-KB SRAM - enables multi-year battery life in sensor nodes and portable UIs. |
| Graphics & Display | MIPI DSI host (2×500 Mbit/s), LTDC, Neo-Chrom GPU, Chrom-ART Accelerator - drives QXGA (2048×1536) displays with hardware-accelerated rotation, scaling, and transparency. |
| Security | PSA Level 3 & SESIP3 certified; TrustZone, HUK, SFI, TF-M support, AES/PKA/HASH coprocessors - meets requirements for secure IoT node authentication and encrypted OTA updates. |
| Analog Peripherals | 2×14-bit ADC (2.5 Msps, oversampling), 12-bit DAC (2 ch), 2 op-amps, 2 comparators - supports precision sensor acquisition and analog actuation in mixed-signal applications. |
Pinout & Package
LQFP64 (10 × 10 mm, 0.5 mm pitch) package with 51 general-purpose I/Os, 4 dedicated power/ground pins, and dedicated function pins including VDDA/VSSA (analog supply), VREF+/- (ADC reference), OSC_IN/OSC_OUT (4–50 MHz crystal), and MIPI DSI lane pairs (CLKP/N, DAT0P/N).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VSS | Main power and ground | Supplies core logic (1.71–3.6 V); decoupling required per datasheet layout guidelines for noise immunity. |
| VDDA, VSSA | Analog domain supply/ground | Isolates ADC/DAC/OPAMP reference paths; must be filtered separately to ensure <1 LSB INL error. |
| PA0–PA15, PB0–PB15, etc. | General-purpose I/Os | Up to 156 fast I/Os; most 5V-tolerant, 14 support independent 1.08–3.6 V supply for interfacing with diverse logic families. |
| OSC_IN / OSC_OUT | External crystal oscillator interface | Supports 4–50 MHz crystals for precise system clock; internal trimming enables ±10 ppm stability over temperature. |
| DSI_CLKP/N, DSI_DAT0P/N | MIPI DSI differential lanes | Drive dual-lane DSI at up to 500 Mbit/s each; require controlled 100-Ω differential impedance routing for signal integrity. |
| LTDC_R0–R7, G0–G7, B0–B7, etc. | RGB parallel output signals | Directly interface 24-bit RGB TFT panels; support programmable polarity, clock phase, and sync timing for flexible panel compatibility. |
Key Features
| Feature | Design Value |
|---|---|
| LPBAM (Low-Power Background Autonomous Mode) | Enables chained peripheral operation (e.g., ADC → DMA → Crypto) in Stop 2 mode without CPU wake-up - reduces active time by >90% in sensor logging cycles. |
| Neo-Chrom GPU (GPU2D) | Accelerates arbitrary-angle rotation, perspective-correct texture mapping, and alpha blending - cuts CPU load by ~70% vs. software rendering for dynamic GUIs. |
| On-the-fly Octo-SPI decryption (OTFDEC) | Decrypts external XIP flash contents in real time using AES-128/256 - enables secure code execution from external memory without runtime overhead. |
| Dual 14-bit ADC with hardware oversampling | Delivers up to 16-bit ENOB at 125 kSPS via digital filtering - eliminates need for external sigma-delta converters in precision measurement systems. |
| Secure Firmware Installation (SFI) | Leverages embedded Root Secure Services (RSS) to validate and install signed firmware images - prevents unauthorized code injection during field updates. |
Applications
| Smart Wearable Display | Industrial HMI Panel |
|---|---|
Use Scenario: Battery-powered smartwatch with always-on color display, biometric sensing, and Bluetooth LE connectivity. IC Role / Device Role / Timing Role: Main application processor managing display refresh (via LTDC + MIPI DSI), sensor fusion (ADC + CORDIC + FMAC), and secure BLE stack (TrustZone-protected crypto). Use Value: 150 nA Shutdown and LPBAM extend battery life to 14+ days; Neo-Chrom GPU enables smooth animated watch faces with <5% CPU utilization. | Use Scenario: Factory-floor operator interface with resistive/capacitive touchscreen, real-time diagnostics, and secure firmware update capability. IC Role / Device Role / Timing Role: Graphics-capable controller driving 800×480 TFT via LTDC, handling touch input (TSC), and executing deterministic control logic (Cortex-M33 + timers). Use Value: Chrom-ART Accelerator ensures tear-free UI transitions; PSA Level 3 certification validates secure remote update compliance for Industry 4.0 deployments. |
| Secure Edge Gateway | Portable Medical Monitor |
Use Scenario: Cellular-connected gateway aggregating sensor data from legacy fieldbus networks and forwarding to cloud with TLS encryption. IC Role / Device Role / Timing Role: Secure network node performing protocol translation (CAN FD, RS-485), TLS 1.3 handshake (SAES + PKA), and authenticated firmware updates (SFI + TF-M). Use Value: Hardware-accelerated crypto achieves 120,000 SecureMark™-TLS score; TrustZone isolates network stack from application logic to prevent lateral attack propagation. | Use Scenario: Handheld ECG/SpO₂ monitor requiring clinical-grade analog acquisition, low-power operation, and HIPAA-compliant data encryption. IC Role / Device Role / Timing Role: Analog front-end controller acquiring ECG signals (14-bit ADC + OPAMP PGA), storing waveform buffers (2.5-MB SRAM), and encrypting data before SD card write (AES + OTFDEC). Use Value: 2.5-Msps ADC with hardware oversampling captures 100+ dB SNR ECG waveforms; 195 nA Standby mode enables >6-month shelf life with coin-cell backup. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-power secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32U575ZIT6 | Same U5A series core and peripherals, but 2-MB Flash, 1-MB SRAM, and TFBGA169 (7×7 mm) package - lacks MIPI DSI and Neo-Chrom GPU. | Targeted at secure sensor hubs and crypto gateways without display requirements. | Select when display acceleration and >2.5-MB SRAM are unnecessary; lower cost and smaller footprint. |
| RA6M5GFP | Arm Cortex-M33 with TrustZone, 1-MB Flash, 512-KB SRAM, no GPU/DSI, but includes CAN FD, USB HS, and 12-bit ADC (1 Msps) - Renesas' Secure IP block replaces PSA Level 3 with RA Security Library. | Suitable for industrial control and motor drive interfaces where CAN FD and USB host are prioritized over graphics. | Choose for CAN FD-centric designs needing Renesas' motor control IP and simpler security model without PSA certification. |
Compared with STM32U5A5RJT6Q, the STM32U575ZIT6 trades display capability and memory for compactness and cost, while the RA6M5GFP offers stronger CAN FD integration and alternate security tooling but lacks MIPI DSI, GPU, and sub-µA low-power modes.
Availability
STM32U5A5RJT6Q is available at Aetrix Electronics and suitable for smart wearable displays, industrial HMI panels, secure edge gateways, and portable medical monitors requiring stable component supply across long product lifecycles.
Supply support for STM32U5A5RJT6Q includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog components for industrial, automotive, and consumer markets.
The STM32U5 series is ST's flagship ultra-low-power MCU line targeting secure, graphics-intensive, battery-operated edge devices - combining Arm TrustZone, advanced power gating, and hardware-accelerated 2D graphics in a single die.
FAQ
What is the maximum operating frequency and associated performance metric of the STM32U5A5RJT6Q?
The STM32U5A5RJT6Q operates at up to 160 MHz and delivers 240 DMIPS (Dhrystone 2.1), achieving 4.09 CoreMark®/MHz and 369 ULPMark™-CP. This performance is sustained with zero-wait-state execution from Flash thanks to its 32-KB instruction cache (ICACHE) and ART Accelerator.
Does the STM32U5A5RJT6Q support external memory interfaces, and if so, which types?
Yes - it supports multiple external memory interfaces: Flexible Static Memory Controller (FSMC) for SRAM, PSRAM, NOR, NAND, and FRAM; two Octo-SPI interfaces for high-speed serial flash/XIP; and one 16-bit HSPI interface running up to 160 MHz for proprietary or legacy parallel memory protocols.
How does the TrustZone implementation on the STM32U5A5RJT6Q differ from standard Cortex-M33 TrustZone?
ST extends standard TrustZone with hardware-enforced peripherals classification (GTZC), secure hide-protection area (HDP) for secret keys, and Root Secure Services (RSS) enabling Secure Firmware Installation (SFI). It also integrates PSA Level 3 and SESIP3 certification - validating resistance to physical, side-channel, and fault injection attacks beyond baseline TrustZone.
What display interfaces are integrated, and what resolutions do they support?
The STM32U5A5RJT6Q integrates MIPI DSI host (dual 500 Mbit/s lanes) and LCD-TFT controller (LTDC). Together, they support QXGA (2048×1536) resolution at 60 Hz with hardware alpha blending, rotation, and perspective-correct texture mapping via the Neo-Chrom GPU and Chrom-ART Accelerator.
STM32U5A5RJT6Q Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- 64-LQFP
- Series:
- STM32U5
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 160MHz
- Connectivity:
- CANbus, EBI/EMI, FIFO, I2C, IrDA, LINbus, MMC/SD, SPI, UART/USART/USB
- Peripherals:
- Brown-out Detect/Reset, Crypto - AES, DMA, PWM, SHA, Temp Sensor, TRNG, WDT
- Number of I/O:
- 47
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 2.5M x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 3.6V
- Data Converters:
- A/D 12x12/14b SAR; D/A 2x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
STM32U5A5RJT6Q FAQ
1.How can I place an order for STM32U5A5RJT6Q through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32U5A5RJT6Q on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32U5A5RJT6Q reliable?
The price and inventory of STM32U5A5RJT6Q are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32U5A5RJT6Q is usually 5 days.
3.What payment methods are accepted for STM32U5A5RJT6Q?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32U5A5RJT6Q transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32U5A5RJT6Q?
STM32U5A5RJT6Q orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32U5A5RJT6Q order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32U5A5RJT6Q?
For technical support, including STM32U5A5RJT6Q datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32U5A5RJT6Q requirements.
6.How does Aetrix verify that STM32U5A5RJT6Q is sourced from the original manufacturer or authorized distributors?
All STM32U5A5RJT6Q products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32U5A5RJT6Q meets industry standards.
7.What is the process for return or replacement of STM32U5A5RJT6Q?
All STM32U5A5RJT6Q units undergo pre-shipment inspection (PSI). If there is an issue with STM32U5A5RJT6Q, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32U5A5RJT6Q part is unused and in its original packaging.
Return procedure for STM32U5A5RJT6Q:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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