STMicroelectronics STM32WB35CCU7A

Overview

STM32WB35CCU7A from STMicroelectronics is a dual-core, multiprotocol wireless 32-bit MCU integrating an Arm® Cortex®-M4 with FPU (64 MHz) and a dedicated Cortex®-M0+ radio controller, supporting Bluetooth® 5.4 and IEEE 802.15.4 PHY/MAC (Thread 1.3/Zigbee® 3.0), with -96 dBm BLE RX sensitivity, +6 dBm programmable TX power, and ultra-low-power operation down to 13 nA shutdown mode. It targets battery-powered IoT edge nodes requiring secure over-the-air updates and regulatory-compliant RF performance.

For engineers reviewing the STM32WB35CCU7A datasheet, STM32WB35CCU7A pinout, STM32WB35CCU7A application, or STM32WB35CCU7A equivalent, this page delivers verified technical context, validated pin functions, real-world low-power use cases, and confirmed alternative parts for Bluetooth/802.15.4 system design - all grounded in ST's DS11929 Rev 18 production data.

Technical Context

The device implements a tightly coupled dual-CPU architecture: the Cortex-M4 handles application logic and security (AES-256, PKA, RNG), while the Cortex-M0+ executes real-time radio stack processing independently. Communication between cores occurs via IPCC and hardware semaphores, enabling deterministic timing for concurrent BLE advertising and application tasks.

Its RF subsystem integrates a 2.4 GHz transceiver with on-die balun, supports GATT caching and EATT, and achieves regulatory compliance (FCC Part 15, ETSI EN 300 328) without external matching components when used with ST's MLPF-WB-01E3 IPD. Power management includes an embedded SMPS with intelligent bypass mode and five BOR thresholds for robust brownout handling across 1.71–3.6 V supply.

Key Specifications

Pinout & Package

STM32WB35CCU7A is housed in a 48-pin UFQFPN package (7 × 7 mm, 0.4 mm pitch), optimized for compact PCB layouts and RF performance. Pin definitions are validated per ST's DS11929 Rev 18 Table 17 (STM32WB35xx pin and ball definitions).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core wireless MCU applications.

Compared with STM32WB35CCU7A, STM32WB55CEU7 offers greater memory scalability and protocol breadth, while nRF52840 DK trades deterministic radio timing for lower BOM cost and simpler software architecture - making each suitable for distinct tiers of wireless system complexity.

Availability

STM32WB35CCU7A is available at Aetrix Electronics and suitable for smart home sensors, industrial gateways, medical wearables, and asset tracking tags requiring stable component supply, long-term lifecycle assurance, and regulatory-compliant RF performance.

Supply support for STM32WB35CCU7A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog products for industrial, automotive, and consumer markets.

The STM32WB series is ST's purpose-built wireless MCU product line targeting secure, ultra-low-power IoT endpoints that require simultaneous Bluetooth Low Energy and IEEE 802.15.4 connectivity - with hardware-enforced separation between application and radio processing.

FAQ

What wireless protocols does STM32WB35CCU7A support natively?

STM32WB35CCU7A natively supports Bluetooth 5.4 (Low Energy only) and IEEE 802.15.4-2011 PHY/MAC layers. It enables certified Thread 1.3 and Zigbee 3.0 protocol stacks via its dual-core architecture - with the Cortex-M0+ executing time-critical radio tasks and the Cortex-M4 managing higher-layer stack logic and application code.

Does STM32WB35CCU7A include an integrated balun, and what is its impact on layout?

Yes, STM32WB35CCU7A integrates a balun within the die, connecting directly to the RF_P/RF_N pins. This eliminates the need for external balun components and discrete matching networks, reducing BOM count by up to 6 passive parts and simplifying PCB layout - especially critical for compact 2.4 GHz antenna designs where impedance control and parasitic minimization are essential.

How does the dual-CPU architecture improve real-time wireless performance?

The Cortex-M0+ CPU is hardwired to the RF subsystem and exclusively handles radio timing-critical operations - including packet reception/transmission, CRC calculation, and automatic ACK generation - independent of the Cortex-M4. This eliminates software-induced jitter, guarantees sub-microsecond interrupt latency for radio events, and prevents application code stalls from disrupting BLE advertising intervals or 802.15.4 channel access timing.

What security features are implemented in hardware for firmware and data protection?

Hardware security includes three independent AES-256 accelerators (for application, BLE, and 802.15.4 stacks), a public-key accelerator (PKA) supporting RSA/ECC/DH, a true random number generator (TRNG), secure firmware installation (SFI) enforcing cryptographic signature verification before stack execution, and PCROP flash protection preventing unauthorized read/write access to sensitive code regions.