My Inquiry
My Account
STMicroelectronics STM32WB55CEU6TR
- Part No.:
- STM32WB55CEU6TR
- Manufacturer:
- STMicroelectronics
- Category:
- RF Transceiver ICs
- Package:
- 48-UFQFN Exposed Pad
- Datasheet:
-
STM32WB55CEU6TR.pdf
- Description:
- IC RF TXRX+MCU 802.15.4 48UFQFPN
- Quantity:
- Payment:
- Shipping:
Inventory:3,898
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
STM32WB55CEU6TR from STMicroelectronics is a dual-core 32-bit wireless MCU integrating an Arm® Cortex®-M4 with FPU (64 MHz) and a dedicated Cortex®-M0+ for real-time radio processing, supporting Bluetooth® 5.4 and IEEE 802.15.4 (Thread/Zigbee® 3.0) on a single die. It delivers -96 dBm RX sensitivity (BLE 1 Mbps), +6 dBm programmable TX output, and ultra-low-power operation down to 13 nA in shutdown mode. It targets secure, battery-operated IoT edge nodes requiring concurrent application logic and certified wireless stack execution.
For engineers reviewing the STM32WB55CEU6TR datasheet, STM32WB55CEU6TR pinout, STM32WB55CEU6TR application, or STM32WB55CEU6TR equivalent, key selection criteria include dual-CPU architecture for BLE/802.15.4 coexistence, integrated SMPS with bypass mode, 1 MB flash with PCROP for secure radio stack isolation, and RF regulatory compliance (FCC/ETSI/ARIB).
Technical Context
The device implements a tightly coupled dual-CPU architecture: the Cortex-M4 handles application firmware and high-level protocol stacks, while the Cortex-M0+ exclusively manages time-critical radio layer operations-including PHY/MAC timing, packet assembly, and GATT caching-ensuring deterministic BLE/802.15.4 behavior without M4 intervention. Inter-processor communication occurs via IPCC with hardware semaphores for resource arbitration.
RF subsystem features an integrated balun, programmable 1 dB-step output power (–20 to +6 dBm), and support for external PA or IPD matching (e.g., MLPF-WB55-02E3). Clocking includes a 32 MHz crystal oscillator with trimming capacitors for RF/CPU synchronization and dual 32 kHz sources (LSE for RTC, LSI2 ±500 ppm for low-power timing).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: Arm Cortex-M4 @ 64 MHz (FPU, ART Accelerator) + Cortex-M0+ @ 32 MHz (dedicated radio layer) |
| Wireless Protocols | Bluetooth 5.4 (LE only), IEEE 802.15.4-2011 PHY/MAC - enabling Thread 1.3 and Zigbee 3.0 certified implementations |
| RF Performance | RX sensitivity: –96 dBm (BLE 1 Mbps), –100 dBm (802.15.4); TX output: programmable –20 to +6 dBm in 1 dB steps |
| Memory | 1 MB flash (sector-protected PCROP), 256 KB SRAM (64 KB with hardware parity), 1 KB OTP, 20×32-bit backup registers |
| Power Modes | 13 nA shutdown, 600 nA standby + RTC + 32 KB RAM, 2.1 µA stop + RTC + 256 KB RAM, <53 µA/MHz active (RF + SMPS on) |
| Supply & Regulation | 1.71–3.6 V operation; embedded SMPS step-down converter with intelligent bypass mode; five selectable BOR thresholds |
| Security | 3× AES-256 engines, HW PKA (RSA/ECC/DH), TRNG, 96-bit unique ID, 64-bit IEEE EUI, Secure Firmware Installation (SFI) |
Pinout & Package
STM32WB55CEU6TR uses a UFQFPN48 package (7 × 7 mm, 0.4 mm pitch) with exposed thermal pad. Pin functions are validated per ST's DS11929 Rev 18, Section 4 ("Pinouts and pin description") and Table 16 ("STM32WB55xx pin and ball definitions").
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VDDRF | Power supply inputs | Separate domains for digital core (VDD), analog (VDDA), and RF (VDDRF) enable noise isolation and optimized regulation |
| PA0–PA15, PB0–PB15, PC0–PC15, PD0–PD2, PE0–PE7 | General-purpose I/Os | Up to 72 fast I/Os; 70 are 5 V-tolerant, supporting mixed-voltage interface design and legacy peripheral integration |
| RF_P, RF_N | Differential RF transceiver interface | Direct connection to integrated balun; requires impedance-matched PCB trace (50 Ω differential) for regulatory-compliant RF performance |
| OSC_IN, OSC_OUT | 32 MHz crystal oscillator terminals | Drive internal RF and CPU clock generation; integrated trimming capacitors eliminate external load caps for simplified layout |
| LSE_IN, LSE_OUT | 32.768 kHz RTC crystal terminals | Enable precise real-time clock operation with external crystal; supports automatic calibration against HSE for long-term accuracy |
| BOOT0 | Boot mode selection | Pulled low for main flash boot; pulled high for system memory bootloader - critical for field OTA recovery and factory programming |
Key Features
| Feature | Design Value |
|---|---|
| Dual-CPU Radio Architecture | Offloads BLE/802.15.4 MAC/PHY timing-critical tasks to Cortex-M0+, freeing M4 for application logic and security processing |
| Integrated RF Front-End | Balun + RF_P/RF_N pins reduce external component count; supports +6 dBm output and external PA expansion for extended range |
| Ultra-Low-Power SMPS | Embedded step-down converter with intelligent bypass mode improves efficiency across load ranges - critical for coin-cell and energy-harvesting designs |
| Secure Firmware Installation (SFI) | Hardware-enforced separation of radio stack and application code in flash; prevents unauthorized modification of certified wireless firmware |
| Hardware Cryptographic Acceleration | AES-256, PKA (ECC/RSA), TRNG, and CRC unit enable full TLS 1.2 handshake and secure OTA updates without CPU overhead |
Applications
| Smart Home Sensor Node | Industrial Wireless Gateway |
|---|---|
|
Use Scenario: Battery-powered temperature/humidity sensor transmitting data every 5 minutes to a central hub via BLE mesh or Thread network. IC Role / Device Role / Timing Role: Dual-core MCU executes sensor fusion algorithm on M4 while M0+ handles BLE advertising, connection management, and GATT caching independently. Use Value: 2.1 µA Stop mode + RTC preserves 10+ year battery life; integrated balun and +6 dBm output ensure reliable link budget in obstructed environments. |
Use Scenario: Edge gateway aggregating Modbus RTU data from 10+ field devices and forwarding to cloud via BLE or 802.15.4-based Thread network. IC Role / Device Role / Timing Role: M4 runs Linux-compatible RTOS and protocol translation; M0+ maintains concurrent BLE and Thread network stacks with EATT and advertising extensions. Use Value: IPCC and hardware semaphores guarantee deterministic inter-CPU messaging; 1 MB flash isolates certified radio stacks from application updates. |
| Medical Wearable Monitor | Asset Tracking Tag |
|
Use Scenario: FDA-classified wearable ECG patch transmitting encrypted biometric data over BLE to smartphone or clinical hub. IC Role / Device Role / Timing Role: M4 performs real-time QRS detection and AES-256 encryption; M0+ handles BLE connection supervision and RSSI-based adaptive power control. Use Value: Hardware PKA accelerates ECC signature generation; TRNG + secure OTP storage meet IEC 62304 cryptographic requirements. |
Use Scenario: GPS-denied indoor asset tag using BLE direction finding (AoA/AoD) or 802.15.4-based location engine for warehouse inventory tracking. IC Role / Device Role / Timing Role: M0+ executes precise RF timing for angle estimation; M4 processes location algorithms and manages multi-protocol beacon scheduling. Use Value: Accurate RSSI and 2 Mbps BLE support enable sub-meter positioning; 72 I/Os allow direct connection to UWB companion ICs or LED indicators. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core wireless MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Nordic nRF52840-QIAA | Single-core ARM Cortex-M4F @ 64 MHz; no dedicated radio CPU; BLE 5.0 + 802.15.4 support via software stack | Higher CPU load during concurrent BLE/802.15.4; no hardware-isolated radio layer; lower RF TX power (+8 dBm max) | Preferred when BLE-only operation dominates and cost sensitivity outweighs dual-CPU determinism |
| TI CC2652R1F | ARM Cortex-M4F @ 48 MHz + dedicated Sensor Controller; BLE 5.1 + 802.15.4; no native Thread/Zigbee 3.0 stack support | Requires external host MCU for full Thread/Zigbee application layer; smaller flash (352 KB) limits complex edge processing | Selected for TI ecosystem integration (SimpleLink SDK) and ultra-low active current (4.4 mA RX) |
Compared with nRF52840-QIAA and CC2652R1F, STM32WB55CEU6TR uniquely provides hardware-isolated dual-CPU execution for certified BLE/Thread coexistence, integrated SMPS for extended battery life, and SFI-enforced radio stack integrity - making it optimal for production-grade, multi-protocol IoT endpoints requiring long-term firmware maintainability.
Availability
STM32WB55CEU6TR is available at Aetrix Electronics and suitable for smart home sensor nodes, industrial wireless gateways, medical wearables, and asset tracking tags requiring stable component supply, long lifecycle assurance, and regulatory-compliant RF certification.
Supply support for STM32WB55CEU6TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in microcontrollers, power management, sensors, and automotive ICs with strong emphasis on industrial and IoT applications.
This part belongs to the STM32WB wireless MCU product line, designed specifically for secure, low-power, multi-protocol IoT edge devices requiring simultaneous BLE and 802.15.4 connectivity with hardware-enforced firmware separation.
FAQ
What wireless protocols does STM32WB55CEU6TR natively support?
STM32WB55CEU6TR natively supports Bluetooth 5.4 (Low Energy only) and IEEE 802.15.4-2011 PHY/MAC layers. These enable certified Thread 1.3 and Zigbee 3.0 protocol stack implementations. The dedicated Cortex-M0+ core executes the radio layer firmware, ensuring deterministic timing for both protocols without M4 interference.
Does STM32WB55CEU6TR require external RF components for basic operation?
No - STM32WB55CEU6TR integrates a balun and supports direct connection to a 50 Ω PCB antenna trace. External components are optional: an IPD (e.g., MLPF-WB55-02E3) improves matching for higher output power or regulatory margin, and an external PA can extend range beyond +6 dBm. Crystal load capacitors are omitted due to internal trimming.
How is secure firmware update implemented on this MCU?
Secure firmware update leverages Secure Firmware Installation (SFI), which enforces hardware-level protection of the radio stack region in flash memory using PCROP (Proprietary Code Read-Out Protection). OTA updates are authenticated via AES-256 and signed with ECC keys accelerated by the PKA engine, ensuring only cryptographically verified images execute on either core.
What is the role of the IPCC peripheral in STM32WB55CEU6TR?
The Inter-Processor Communication Controller (IPCC) provides a hardware mailbox interface between the Cortex-M4 and Cortex-M0+ cores. It enables zero-copy message passing for BLE/802.15.4 stack commands and events, synchronized via hardware semaphores to prevent race conditions - eliminating software polling and reducing inter-core latency to sub-microsecond levels.
STM32WB55CEU6TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- STM32WB
- Package/Case:
- 48-UFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- TxRx + MCU
- RF Family/Standard:
- 802.15.4, Bluetooth
- Protocol:
- Bluetooth v5.3, Thread, Zigbee®
- Modulation:
- GFSK
- Frequency:
- 2.405GHz ~ 2.48GHz
- Data Rate (Max):
- 2Mbps
- Power - Output:
- 6dBm
- Sensitivity:
- -100dBm
- Memory Size:
- 512kB Flash, 256kB SRAM
- Serial Interfaces:
- ADC, I2C, SPI, UART, USART, USB
- GPIO:
- 30
- Voltage - Supply:
- 1.71V ~ 3.6V
- Current - Receiving:
- 4.5mA ~ 7.9mA
- Current - Transmitting:
- 5.2mA ~ 12.7mA
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 48-UFQFPN (7x7)
STM32WB55CEU6TR FAQ
1.How can I place an order for STM32WB55CEU6TR through Aetrix?
Please submit a Request for Quotation (RFQ) for STM32WB55CEU6TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for STM32WB55CEU6TR reliable?
The price and inventory of STM32WB55CEU6TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for STM32WB55CEU6TR is usually 5 days.
3.What payment methods are accepted for STM32WB55CEU6TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for STM32WB55CEU6TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for STM32WB55CEU6TR?
STM32WB55CEU6TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your STM32WB55CEU6TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for STM32WB55CEU6TR?
For technical support, including STM32WB55CEU6TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your STM32WB55CEU6TR requirements.
6.How does Aetrix verify that STM32WB55CEU6TR is sourced from the original manufacturer or authorized distributors?
All STM32WB55CEU6TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that STM32WB55CEU6TR meets industry standards.
7.What is the process for return or replacement of STM32WB55CEU6TR?
All STM32WB55CEU6TR units undergo pre-shipment inspection (PSI). If there is an issue with STM32WB55CEU6TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The STM32WB55CEU6TR part is unused and in its original packaging.
Return procedure for STM32WB55CEU6TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
STM32WB55CEU6TR Tags
-
ESP32-D0WD-V3
Espressif Systems
-
ESP8266EX
Espressif Systems
-
ESP32-S3
Espressif Systems
-
NRF24L01P-R7
Nordic Semiconductor ASA
-
NRF24L01P-R
Nordic Semiconductor ASA
-
ESP32-U4WDH
Espressif Systems
-
DA14531-00000OG2
Renesas
-
ESP32-C6FH4
Espressif Systems
-
DA14531-00000FX2
Renesas
-
NRF24L01P-T
Nordic Semiconductor ASA
-
NRF52810-QCAA-R
Nordic Semiconductor ASA
-
ESP32-S3FN8
Espressif Systems
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
